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Merge pull request #844 from pascalgouedo/dev_dd_pgo_doc
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User Manual updates
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@davideschiavone
davideschiavone authored Aug 4, 2023
2 parents c02a42b + 0f36837 commit 73ff0c1
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62 changes: 32 additions & 30 deletions docs/source/control_status_registers.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -375,7 +375,7 @@ Detailed:
+=============+===========+===========================================+
| 31:2 | URO | Start Address of the HWLoop 0/1. |
+-------------+-----------+-------------------------------------------+
| 1:0 | URO | Hardwired to 0. |
| 1:0 | URO | 0 |
+-------------+-----------+-------------------------------------------+

HWLoop End Address 0/1 (``lpend0/1``)
Expand All @@ -396,7 +396,7 @@ Detailed:
+=============+===========+===========================================+
| 31:2 | URO | End Address of the HWLoop 0/1. |
+-------------+-----------+-------------------------------------------+
| 1:0 | URO | Hardwired to 0. |
| 1:0 | URO | 0 |
+-------------+-----------+-------------------------------------------+

HWLoop Count Address 0/1 (``lpcount0/1``)
Expand Down Expand Up @@ -441,9 +441,9 @@ Detailed:
| | | |
| | | SD set to 1 if **FS** = 11 meaning Floating point State is dirty so save/restore is needed in case of context switch. |
| | | |
| | | Hardwired to 0 if ``FPU`` = 0 or (``FPU`` = 1 and ``ZFINX`` = 1). |
| | | 0 if ``FPU`` = 0 or (``FPU`` = 1 and ``ZFINX`` = 1). |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 30:15 | RO | Unimplemented, hardwired to 0. |
| 30:15 | RO | 0, Unimplemented. |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 14:13 | RW | **FS:** Floating point State |
| | | |
Expand All @@ -455,27 +455,27 @@ Detailed:
| | | |
| | | 11 = Dirty |
| | | |
| | | Hardwired to 0 if ``FPU`` = 0 or (``FPU`` = 1 and ``ZFINX`` = 1). |
| | | 0 if ``FPU`` = 0 or (``FPU`` = 1 and ``ZFINX`` = 1). |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 12:11 | RO | **MPP:** Machine Previous Priviledge mode |
| | | |
| | | Hardwired to 11 when the user mode is not enabled. |
| | | 11 when the user mode is not enabled. |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 10:8 | RO | Unimplemented, hardwired to 0. |
| 10:8 | RO | 0, Unimplemented. |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 7 | RO | **MPIE:** Machine Previous Interrupt Enable |
| | | |
| | | When an exception is encountered, MPIE will be set to MIE. |
| | | When the mret instruction is executed, the value of MPIE will be stored to MIE. |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 6:4 | RO | Unimplemented, hardwired to 0. |
| 6:4 | RO | 0, Unimplemented. |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 3 | RW | **MIE:** Machine Interrupt Enable |
| | | |
| | | If you want to enable interrupt handling in your exception handler, |
| | | set the Interrupt Enable MIE to 1 inside your handler code. |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 2:0 | RO | Unimplemented, hardwired to 0. |
| 2:0 | RO | 0, Unimplemented. |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+

.. only:: USER
Expand Down Expand Up @@ -519,25 +519,25 @@ Detailed:
| | | |
| | | Set bit x to enable interrupt irq_i[x] (x between 16 and 31). |
+-------------+-----------+------------------------------------------------------------------------------------------+
| 15:12 | RO | Hardwired to 0. |
| 15:12 | RO | 0 |
+-------------+-----------+------------------------------------------------------------------------------------------+
| 11 | RW | **MEIE:** Machine External Interrupt Enable |
| | | |
| | | If set, irq_i[11] is enabled. |
+-------------+-----------+------------------------------------------------------------------------------------------+
| 10:8 | RO | Hardwired to 0. |
| 10:8 | RO | 0 |
+-------------+-----------+------------------------------------------------------------------------------------------+
| 7 | RW | **MTIE:** Machine Timer Interrupt Enable |
| | | |
| | | If set, irq_i[7] is enabled. |
+-------------+-----------+------------------------------------------------------------------------------------------+
| 6:4 | RO | Hardwired to 0. |
| 6:4 | RO | 0 |
+-------------+-----------+------------------------------------------------------------------------------------------+
| 3 | RW | **MSIE:** Machine Software Interrupt Enable |
| | | |
| | | If set, irq_i[3] is enabled. |
+-------------+-----------+------------------------------------------------------------------------------------------+
| 2:0 | RO | Hardwired to 0. |
| 2:0 | RO | 0 |
+-------------+-----------+------------------------------------------------------------------------------------------+

.. _csr-mtvec:
Expand Down Expand Up @@ -695,25 +695,25 @@ Detailed:
| | | |
| | | If bit x is set, interrupt irq_i[x] is pending (x between 16 and 31). |
+-------------+-----------+---------------------------------------------------------------------------------------------------+
| 15:12 | RO | Hardwired to 0. |
| 15:12 | RO | 0 |
+-------------+-----------+---------------------------------------------------------------------------------------------------+
| 11 | RO | **MEIP:** Machine External Interrupt Pending |
| | | |
| | | If set, irq_i[11] is pending. |
+-------------+-----------+---------------------------------------------------------------------------------------------------+
| 10:8 | RO | Hardwired to 0. |
| 10:8 | RO | 0 |
+-------------+-----------+---------------------------------------------------------------------------------------------------+
| 7 | RO | **MTIP:** Machine Timer Interrupt Pending |
| | | |
| | | If set, irq_i[7] is pending. |
+-------------+-----------+---------------------------------------------------------------------------------------------------+
| 6:4 | RO | Hardwired to 0. |
| 6:4 | RO | 0 |
+-------------+-----------+---------------------------------------------------------------------------------------------------+
| 3 | RO | **MSIP:** Machine Software Interrupt Pending |
| | | |
| | | If set, irq_i[3] is pending. |
+-------------+-----------+---------------------------------------------------------------------------------------------------+
| 2:0 | RO | Hardwired to 0. |
| 2:0 | RO | 0 |
+-------------+-----------+---------------------------------------------------------------------------------------------------+

Trigger CSRs
Expand Down Expand Up @@ -1504,19 +1504,21 @@ Machine Implementation ID (``mimpid``)

CSR Address: 0xF13

Reset Value: 0x0000_0000
Reset Value: Defined

Detailed:

.. table::
:widths: 15 15 70
:class: no-scrollbar-table

+-------------+-----------+------------------------------------------------------------------------+
| **Bit #** | **Mode** | **Description** |
+=============+===========+========================================================================+
| 31:0 | RO | 0 |
+-------------+-----------+------------------------------------------------------------------------+
+-------------+-----------+-------------------------------------------------------------------------+
| **Bit #** | **Mode** | **Description** |
+=============+===========+=========================================================================+
| 31 : 1 | RO | 0 |
+-------------+-----------+-------------------------------------------------------------------------+
| 0 | RO | 1 if ``FPU`` = 1 or ``COREV_PULP`` = 1 or ``COREV_CLUSTER`` = 1 else 0. |
+-------------+-----------+-------------------------------------------------------------------------+

.. _csr-mhartid:

Expand Down Expand Up @@ -1714,10 +1716,10 @@ Reset Value: Defined
:widths: 15 15 70
:class: no-scrollbar-table

+-------------+-----------+----------------------------------------------------------------+
| **Bit #** | **Mode** | **Description** |
+=============+===========+================================================================+
| 31:1 | RO | Hardwired to 0. |
+-------------+-----------+----------------------------------------------------------------+
| 0 | RO | 1 if ``FPU`` = 1 and ``ZFINX`` = 1 else 0. |
+-------------+-----------+----------------------------------------------------------------+
+-------------+-----------+---------------------------------------------------+
| **Bit #** | **Mode** | **Description** |
+=============+===========+===================================================+
| 31:1 | RO | 0 |
+-------------+-----------+---------------------------------------------------+
| 0 | RO | 1 if ``FPU`` = 1 and ``ZFINX`` = 1 else 0. |
+-------------+-----------+---------------------------------------------------+
9 changes: 3 additions & 6 deletions docs/source/core_versions.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -129,8 +129,8 @@ It refers to the CV32E40P core verified with the following parameters:
+---------------------------+-------+
| ``PULP_CLUSTER`` | 0 |
+---------------------------+-------+
| ``NUM_MHPMCOUNTERS`` | 1 |
+---------------------------+-------+

Verification of cv32e40p_v1.0.0 has been done with only following value for ``NUM_MHPMCOUNTERS`` parameter: ``NUM_MHPMCOUNTERS`` == 1.

The list of open (waived) issues at the time of applying the cv32e40p_v1.0.0 tag can be found at:

Expand Down Expand Up @@ -165,16 +165,13 @@ When parameters are set with the exact same values than for cv32e40p_v1.0.0 rele
+---------------------------+-------+
| ``COREV_CLUSTER`` | 0 |
+---------------------------+-------+
| ``NUM_MHPMCOUNTERS`` | 1 |
+---------------------------+-------+

mimpid = 1
~~~~~~~~~~

When one parameter is set with a different value than for cv32e40p_v1.0.0 release then ``mimpid`` value is equal to ``1``.

This means either ``FPU``, ``ZFINX``, ``COREV_PULP`` or ``COREV_CLUSTER`` is set to 1.
Or ``NUM_MHPMCOUNTERS`` is set to a value greater than 1.
This means either ``FPU``, ``COREV_PULP`` or ``COREV_CLUSTER`` is set to 1.

.. The list of open (waived) issues at the time of applying the cv32e40p_v1.0.0 tag can be found at:
Expand Down
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