Some Core RTL bug fixes and CVFPU 0.8.1 vendorization #860
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added 7 commits
August 29, 2023 15:11
Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
Signed-off-by: Pascal Gouedo <[email protected]>
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Component:RTL
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Status:Do-not-merge
- Fix Underflow flag for MUL and DIV/SQRT operations (openhwgroup#94 openhwgroup#726 openhwgroup#729) - Fix for Float to Int conversion (openhwgroup#97 openhwgroup#83 openhwgroup#727) - Fixed unnecessary trailing semicolon (openhwgroup#99) Signed-off-by: Pascal Gouedo <[email protected]>
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Status:Do-not-merge
davideschiavone
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Aug 30, 2023
This was referenced Oct 9, 2023
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Fix Underflow flag for MUL and DIV/SQRT operations (riscv_compliance_tests error: "I-SB-01.S" and "I-SH-01.S" not passed #94 F multiply accumulate instructions set underflow flag of fflags wrongly #726 FMUL.S instructions set underflow flag of fflags wrongly #729)
Fix for Float to Int conversion (Fix newlib versions #97 Decoder bug for casting instruction FP to INT #83 FCVT.W.S instructions set invalid operation flag of fflags wrongly #727)
Fixed unnecessary trailing semicolon (align design to spike simulator on setting mpie to 1'b0 on mret #99)