Automatic PR dev->master

bhv/cv32e40p_rvfi.sv

@@ -1430,7 +1430,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
       s_new_valid_insn = r_pipe_freeze_trace.id_valid && r_pipe_freeze_trace.is_decoding;// && !r_pipe_freeze_trace.apu_rvalid;
 
-      s_wb_valid_adjusted = r_pipe_freeze_trace.wb_valid && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == FLUSH_EX) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_FLUSH) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_ID) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_IF));// && !r_pipe_freeze_trace.apu_rvalid;;
+      s_wb_valid_adjusted = r_pipe_freeze_trace.wb_valid && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == FLUSH_EX) || (r_pipe_freeze_trace.ctrl_fsm_cs == FLUSH_WB) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_FLUSH) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_ID) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_IF));// && !r_pipe_freeze_trace.apu_rvalid;;
       s_ex_reg_we_adjusted = r_pipe_freeze_trace.ex_reg_we && r_pipe_freeze_trace.mult_ready && r_pipe_freeze_trace.alu_ready && r_pipe_freeze_trace.lsu_ready_ex && !s_apu_to_alu_port;
       s_rf_we_wb_adjusted = r_pipe_freeze_trace.rf_we_wb && (~r_pipe_freeze_trace.data_misaligned_ex && r_pipe_freeze_trace.wb_ready) && (!s_apu_to_lsu_port || r_pipe_freeze_trace.wb_contention_lsu);
 

bhv/pipe_freeze_trace.sv

@@ -367,7 +367,10 @@ function compute_csr_we();
         r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1;
       end
       CSR_FRM:       r_pipe_freeze_trace.csr.frm_we = 1'b1;
-      CSR_FCSR:      r_pipe_freeze_trace.csr.fcsr_we = 1'b1;
+      CSR_FCSR: begin
+        r_pipe_freeze_trace.csr.fcsr_we = 1'b1;
+        r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1;
+      end
       CSR_DPC:       r_pipe_freeze_trace.csr.dpc_we = 1'b1;
       CSR_DSCRATCH0: r_pipe_freeze_trace.csr.dscratch0_we = 1'b1;
       CSR_DSCRATCH1: r_pipe_freeze_trace.csr.dscratch1_we = 1'b1;

docs/source/corev_hw_loop.rst

@@ -90,12 +90,9 @@ is that it greatly simplifies compiler optimization (relative to basic blocks ma
 In order to use hardware loops, the compiler needs to setup the loops beforehand with cv.start/i, cv.end/i, cv.count/i or cv.setup/i instructions.
 The compiler will use HWLoop automatically whenever possible without the need of assembly.
 
-For debugging and context switches, the hardware loop registers are mapped into the CSR custom read-only address space.
+For debugging, interrupts and context switches, the hardware loop registers are mapped into the CSR custom read-only address space.
 To read them csrr instructions should be used and to write them register flavour of hardware loop instructions should be used.
 Using csrw instructions to write hardware loop registers will generate an illegal instruction exception.
-
-Since hardware loop feature could be used in interrupt routine/handler, the registers have
-to be saved (resp. restored) at the beginning (resp. end) of the interrupt routine together with the general purpose registers.
 The CSR HWLoop registers are described in the :ref:`cs-registers` section.
 
 Below an assembly code example of a nested HWLoop that computes a matrix addition.
@@ -138,3 +135,50 @@ it is executed 10x10 times. Whereas the outermost loop, from startO to (endO - 4
 executes 10 times the innermost loop and adds 2 to the register %[j].
 At the end of the loop, the register %[i] contains 300 and the register %[j] contains 20.
 
+.. _hwloop-exceptions_handlers:
+
+Hardware loops impact on application, exceptions handlers and debugger
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Application and ebreak/ecall exception handlers
+-----------------------------------------------
+
+When an ebreak or an ecall instruction is used in an application, special care should be given for those instruction handlers in case they are placed as the last instruction of an HWLoop.
+Those handlers should manage MEPC and lpcountX CSRs updates because an hw loop early-exit could happen if not done.
+
+At the end of the handlers after restoring the context/CSRs, a piece of smart code should be added with following highest to lowest order of priority:
+
+1. if MEPC = lpend0 - 4 and lpcount0 > 1 then MPEC should be set to lpstart0 and lpcount0 should be decremented by 1,
+2. else if MEPC = lpend0 - 4 and lpcount0 = 1 then MPEC should be incremented by 4 and lpcount0 should be decremented by 1,
+3. else if MEPC = lpend1 - 4 and lpcount1 > 1 then MPEC should be set to lpstart1 and lpcount1 should be decremented by 1,
+4. else if MEPC = lpend1 - 4 and lpcount1 = 1 then MPEC should be incremented by 4 and lpcount1 should be decremented by 1,
+5. else if (lpstart0 <= MEPC < lpend0 - 4) or (lpstart1 <= MEPC < lpend1 - 4) then MPEC should be incremented by 4,
+6. else if instruction at MEPC location is either ecall or ebreak then MPEC should be incremented by 4,
+7. else if instruction at MEPC location location is c.ebreak then MPEC should be incremented by 2.
+
+The 2 last cases are the standard ones when ebreak/ecall are not inside an HWLopp.
+
+Interrupt handlers
+------------------
+
+When an interrupt is happening on the last HWLoop instruction, its execution is cancelled, its address is saved in MEPC and its execution will be resumed when returning from interrupt handler.
+There is nothing special to be done in those interrupt handlers with respect to MEPC and lpcountX updates, they will be correctly managed by design when executing this last HWLoop instruction after interrupt handler execution.
+
+Moreover since hardware loop could be used in interrupt routine, the registers have to be saved (resp. restored) at the beginning (resp. end) of the interrupt routine together with the general purpose registers.
+
+Illegal instruction exception handler
+-------------------------------------
+
+Depending if an application is going to resume or not after Illegal instruction exception handler, same MEPC/HWLoops CSRs management than ebreak/ecall could be necessary.
+
+Debugger
+--------
+
+If ebreak is used to enter in Debug Mode (:ref:`ebreak_scenario_2`) and put at the last instruction location of an HWLoop (not very likely to happen), same management than above should be done but on DPC rather than on MEPC.
+
+When ebreak instruction is used as Software Breakpoint by a debugger when in debug mode and is placed at the last instruction location of an HWLoop in instruction memory, no special management is foreseen.
+When executing the Software Breakpoint/ebreak instruction, control is given back to the debugger which will manage the different cases.
+For instance in Single-Step case, original instruction is put back in instruction memory, a Single-Step command is executed on this last instruction (with desgin updating PC and lpcountX to correct values) and Software Breakpoint/ebreak is put back by the debugger in memory.
+
+When ecall instruction is used by a debugger to execute System Calls and is placed at the last instruction location of an HWLoop in instruction memory, debugger ecall handler in debug rom should do the same than described above for application case.
+

docs/source/debug.rst

@@ -162,6 +162,8 @@ The EBREAK instruction description is distributed across several RISC-V specific
 `RISC-V Priveleged Specification <https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMFDQC-and-Priv-v1.11>`_,
 `RISC-V ISA <https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC>`_. The following is a summary of the behavior for three common scenarios.
 
+.. _ebreak_scenario_1:
+
 Scenario 1 : Enter Exception
 """"""""""""""""""""""""""""
 
@@ -173,10 +175,14 @@ Executing the EBREAK instruction when the core is **not** in Debug Mode and the
 To properly return from the exception, the ebreak handler will need to increment the MEPC to the next instruction.
 This requires querying the size of the ebreak instruction that was used to enter the exception (16 bit c.ebreak or 32 bit ebreak). 
 
+As mentioned in :ref:`hwloop-exceptions_handlers`, some additional cases exist for MEPC update when ebreak is the last instruction of an Hardware Loop.
+
 .. note::
 
   The CV32E40P does not support MTVAL CSR register which would have saved the value of the instruction for exceptions. This may be supported on a future core.
 
+.. _ebreak_scenario_2:
+
 Scenario 2 : Enter Debug Mode
 """""""""""""""""""""""""""""
 
@@ -187,11 +193,15 @@ Executing the EBREAK instruction when the core is **not** in Debug Mode and the
 
 Similar to the exception scenario above, the debugger will need to increment the DPC to the next instruction before returning from Debug Mode.
 
+There is no forseseen situtation where it would be needed to enter in Debug Mode only on the last instruction of an Hardware Loop but just in case this is mentioned in :ref:`hwloop-exceptions_handlers` as well.
+
 .. note::
 
   The default value of DCSR.EBREAKM is 0 and the DCSR is only accessible in Debug Mode. To enter Debug Mode from EBREAK,
   the user will first need to enter Debug Mode through some other means, such as from the external ``debug_req_i``, and set DCSR.EBREAKM.
 
+.. _ebreak_scenario_3:
+
 Scenario 3 : Exit Program Buffer & Restart Debug Code
 """""""""""""""""""""""""""""""""""""""""""""""""""""
 

docs/source/pipeline.rst

@@ -150,7 +150,7 @@ The cycle counts assume zero stall on the instruction-side interface and zero st
   | Comparison, Conversion |                                      | If there are enough instructions between FPU one and        |
   | or Classify            |                                      | the instruction using the result then cycle number is 1.    |
   +------------------------+--------------------------------------+ "Enough instruction" number is either FPU_ADDMUL_LAT,       |
-  | Single Precision       | 1..12                                | FPU_OTHERS_LAT or 11.                                       |
+  | Single Precision       | 1..19                                | FPU_OTHERS_LAT or 11.                                       |
   | Floating-Point         |                                      | If there are no instruction in between then cycle number is |
   | Division and           |                                      | the maximum value for each category.                        |
   | Square-Root            |                                      |                                                             |