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This repository has been archived by the owner on Nov 24, 2023. It is now read-only.

Issues: openhwgroup/cv32e41p

9 Open 3 Closed
9 Open 3 Closed
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Issues list

Undeclared/unconnected Signals in merged_decoder and id_stage
#27 opened Feb 24, 2023 by Westwood68
1
Move register id decoding from decode to fetch stage
#14 opened Feb 7, 2022 by abukharmeh
2
Remove PULP
#13 opened Feb 7, 2022 by abukharmeh
2
Change the implementation of table jump instructions
#12 opened Feb 7, 2022 by abukharmeh
1
Update Zc to Version 0.70
#11 opened Feb 7, 2022 by abukharmeh
can not find docs for 41p
#8 opened Aug 27, 2021 by simon5656
2
Implement the Zce ISA extension bug Something isn't working
#4 opened Jun 23, 2021 by davideschiavone
3 tasks
@tariqkurd-repo
Change PULP_ZFINX ISA to the RISC-V ZFINX ISA bug Something isn't working
#3 opened Jun 23, 2021 by davideschiavone
3 tasks
@tariqkurd-repo
Make and Build CV32E41P Documentation documentation Improvements or additions to documentation
#1 opened Jun 23, 2021 by davideschiavone
@davideschiavone
ProTip! Find all open issues with in progress development work with linked:pr.