Preliminary OS support

.gitignore

@@ -0,0 +1,2 @@
+test_benches/verilator/build
+

README.md

@@ -1,6 +1,5 @@
 # CVA5
-
-CVA5 is a 32-bit RISC-V processor designed for FPGAs supporting the Multiply/Divide and Double-precision Floating-Point extensions (RV32IMD).  The processor is written in SystemVerilog and has been designed to be both highly extensible and highly configurable.
+CVA5 is a 32-bit RISC-V processor designed for FPGAs supporting the Multiply/Divide, Atomic, and Floating-Point extensions (RV32IMAFD).  The processor is written in SystemVerilog and has been designed to be both highly extensible and highly configurable.
 
 
 The CVA5 is derived from the Taiga Project from Simon Fraser University.
@@ -16,7 +15,6 @@ For up-to-date documentation, as well as an automated build environment setup, r
 
 
 ## License
-
 CVA5 is licensed under the Solderpad License, Version 2.1 ( http://solderpad.org/licenses/SHL-2.1/ ).  Solderpad is an extension of the Apache License, and many contributions to CVA5 were made under Apache Version 2.0 ( https://www.apache.org/licenses/LICENSE-2.0 )
 
 
@@ -25,10 +23,14 @@ A zedboard configuration is provided under the examples directory along with too
 
 
 ## Publications
+C. Keilbart, Y. Gao, M. Chua, E. Matthews, S. J. Wilton, and L. Shannon, “Designing an IEEE-Compliant FPU that Supports Configurable Precision for Soft Processors,” ACM Trans. Reconfgurable Technol. Syst., vol. 17, no. 2, Apr. 2024.
+doi: [https://doi.org/10.1145/3650036](https://doi.org/10.1145/3650036)
+
 E. Matthews, A. Lu, Z. Fang and L. Shannon, "Rethinking Integer Divider Design for FPGA-Based Soft-Processors," 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), San Diego, CA, USA, 2019, pp. 289-297.
 doi: [https://doi.org/10.1109/FCCM.2019.00046](https://doi.org/10.1109/FCCM.2019.00046)
 
 E. Matthews, Z. Aguila and L. Shannon, "Evaluating the Performance Efficiency of a Soft-Processor, Variable-Length, Parallel-Execution-Unit Architecture for FPGAs Using the RISC-V ISA," 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boulder, CO, 2018, pp. 1-8.
 doi: [https://doi.org/10.1109/FCCM.2018.00010](https://doi.org/10.1109/FCCM.2018.00010)
 
-E. Matthews and L. Shannon, "TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features," 2017 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium, 2017. [https://doi.org/10.23919/FPL.2017.8056766](https://doi.org/10.23919/FPL.2017.8056766)
+E. Matthews and L. Shannon, "TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features," 2017 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium, 2017. 
+doi: [https://doi.org/10.23919/FPL.2017.8056766](https://doi.org/10.23919/FPL.2017.8056766)

core/common_components/cva5_fifo.sv

@@ -27,10 +27,6 @@
  */
 module cva5_fifo
 
-    import cva5_config::*;
-    import riscv_types::*;
-    import cva5_types::*;
-
     #(
         parameter type DATA_TYPE = logic,
         parameter FIFO_DEPTH = 4
@@ -49,8 +45,10 @@ module cva5_fifo
         always_ff @ (posedge clk) begin
             if (rst)
                 fifo.valid <= 0;
-            else
-                fifo.valid <= fifo.push | (fifo.valid & ~fifo.pop);
+            else if (fifo.push & ~fifo.pop)
+                fifo.valid <= 1;
+            else if (fifo.pop & ~fifo.push)
+                fifo.valid <= 0;
         end
         assign fifo.full = fifo.valid;
 
@@ -134,6 +132,6 @@ module cva5_fifo
     fifo_potenial_push_overflow_assertion:
         assert property (@(posedge clk) disable iff (rst) fifo.potential_push |-> (~fifo.full | fifo.pop)) else $error("potential push overflow");
     fifo_underflow_assertion:
-        assert property (@(posedge clk) disable iff (rst) fifo.pop |-> fifo.valid) else $error("underflow");
+        assert property (@(posedge clk) disable iff (rst) fifo.pop |-> (fifo.valid | fifo.push)) else $error("underflow");
 
 endmodule

core/common_components/lfsr.sv

@@ -68,7 +68,7 @@ module lfsr
     logic feedback;
     ////////////////////////////////////////////////////
     //Implementation
-    generate if (WIDTH == 2) begin : gen_width_two
+    generate if (WIDTH <= 2) begin : gen_width_one_or_two
         assign feedback = ~value[WIDTH-1];
     end
     else begin : gen_width_three_plus
@@ -84,8 +84,10 @@ module lfsr
     always_ff @ (posedge clk) begin
         if (NEEDS_RESET & rst)
             value <= '0;
-        else if (en)
-            value <= {value[WIDTH-2:0], feedback};
+        else if (en) begin
+            value <= value << 1;
+            value[0] <= feedback;
+        end
     end
 
 endmodule

core/common_components/one_hot_mux.sv

@@ -0,0 +1,86 @@
+/*
+ * Copyright © 2024 Chris Keilbart
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Initial code developed under the supervision of Dr. Lesley Shannon,
+ * Reconfigurable Computing Lab, Simon Fraser University.
+ *
+ * Author(s):
+ *             Chris Keilbart <[email protected]>
+ */
+
+
+module one_hot_mux
+    #(
+        parameter OPTIONS = 5,
+        parameter type DATA_TYPE = logic
+    )
+    (
+        //Only used for assertions
+        input logic clk,
+        input logic rst,
+
+        input logic[OPTIONS-1:0] one_hot,
+        input DATA_TYPE[OPTIONS-1:0] choices,
+        output DATA_TYPE sel
+    );
+
+    //Casting to eliminate warnings
+    typedef logic[$bits(DATA_TYPE)-1:0] casted_t;
+    casted_t[OPTIONS-1:0] choices_casted;
+    casted_t sel_casted;
+
+    ////////////////////////////////////////////////////
+    //Implementation
+    //Cheaper than converting ohot -> int and indexing
+    always_comb begin
+        for (int i = 0; i < OPTIONS; i++)
+            choices_casted[i] = casted_t'(choices[i]);
+        sel = DATA_TYPE'(sel_casted);
+    end
+
+    generate if (OPTIONS == 1) begin : gen_no_mux
+        assign sel_casted = choices_casted[0];
+    end else begin : gen_mux
+        always_comb begin
+            sel_casted = '0;
+            for (int i = 0; i < OPTIONS; i++)
+                if (one_hot[i]) sel_casted |= choices_casted[i];
+        end
+    end endgenerate
+
+    ////////////////////////////////////////////////////
+    //Assertions
+    //Support inputs that aren't one hot as long as they are identical
+    logic supported_inputs;
+    logic saw_first;
+    casted_t queried_input;
+    always_comb begin
+        supported_inputs = 1;
+        saw_first = 0;
+        queried_input = 'x;
+        for (int i = 0; i < OPTIONS; i++) begin
+            if (one_hot[i]) begin
+                supported_inputs |= ~saw_first | (queried_input == choices_casted[i]);
+                saw_first = 1;
+                queried_input = choices_casted[i];
+            end
+        end
+    end
+
+    ohot_assertion:
+        assert property (@(posedge clk) disable iff (rst) supported_inputs)
+        else $error("Selection mux not one hot");
+
+endmodule

core/common_components/ram/sdp_ram.sv

@@ -0,0 +1,86 @@
+/*
+ * Copyright © 2024 Chris Keilbart, Lesley Shannon
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Initial code developed under the supervision of Dr. Lesley Shannon,
+ * Reconfigurable Computing Lab, Simon Fraser University.
+ *
+ * Author(s):
+ *             Chris Keilbart <[email protected]>
+ */
+
+module sdp_ram
+
+    #(
+        parameter ADDR_WIDTH = 10,
+        parameter NUM_COL = 4, //Number of independently writeable components
+        parameter COL_WIDTH = 16, //Width the "byte" enable controls
+        parameter DATA_WIDTH = COL_WIDTH*NUM_COL, //Do not set this to anything else
+        parameter PIPELINE_DEPTH = 1, //Depth of the output pipeline, is latency in clock cycles
+        parameter CASCADE_DEPTH = 4 //Maximum depth of the memory block cascade
+    )
+    (
+        input logic clk,
+        //Port A
+        input logic a_en,
+        input logic[NUM_COL-1:0] a_wbe,
+        input logic[DATA_WIDTH-1:0] a_wdata,
+        input logic[ADDR_WIDTH-1:0] a_addr,
+
+        //Port B
+        input logic b_en,
+        input logic[ADDR_WIDTH-1:0] b_addr,
+        output logic[DATA_WIDTH-1:0] b_rdata
+    );
+
+    (* cascade_height = CASCADE_DEPTH, ramstyle = "no_rw_check" *) //Higher depths use less resources but are slower
+    logic[DATA_WIDTH-1:0] mem[(1<<ADDR_WIDTH)-1:0];
+
+    initial mem = '{default: '0};
+
+    //A write
+    always_ff @(posedge clk) begin
+        for (int i = 0; i < NUM_COL; i++) begin
+            if (a_en & a_wbe[i])
+                mem[a_addr][i*COL_WIDTH +: COL_WIDTH] <= a_wdata[i*COL_WIDTH +: COL_WIDTH];
+        end
+    end
+
+
+    //B read
+    logic[DATA_WIDTH-1:0] b_ram_output;
+    always_ff @(posedge clk) begin
+        if (b_en)
+            b_ram_output <= mem[b_addr];
+    end
+
+    //B pipeline
+    generate if (PIPELINE_DEPTH > 0) begin : gen_b_pipeline
+        logic[DATA_WIDTH-1:0] b_data_pipeline[PIPELINE_DEPTH-1:0];
+        logic[PIPELINE_DEPTH-1:0] b_en_pipeline;
+
+        always_ff @(posedge clk) begin
+            for (int i = 0; i < PIPELINE_DEPTH; i++) begin
+                b_en_pipeline[i] <= i == 0 ? b_en : b_en_pipeline[i-1];
+                if (b_en_pipeline[i])
+                    b_data_pipeline[i] <= i == 0 ? b_ram_output : b_data_pipeline[i-1];
+            end
+        end
+        assign b_rdata = b_data_pipeline[PIPELINE_DEPTH-1];
+    end
+    else begin : gen_b_transparent_output
+        assign b_rdata = b_ram_output;
+    end endgenerate
+
+endmodule

core/common_components/ram/sdp_ram_padded.sv

@@ -0,0 +1,87 @@
+/*
+ * Copyright © 2024 Chris Keilbart, Lesley Shannon
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Initial code developed under the supervision of Dr. Lesley Shannon,
+ * Reconfigurable Computing Lab, Simon Fraser University.
+ *
+ * Author(s):
+ *             Chris Keilbart <[email protected]>
+ */
+
+module sdp_ram_padded
+
+    #(
+        parameter ADDR_WIDTH = 10,
+        parameter NUM_COL = 4, //Number of independently writeable components
+        parameter COL_WIDTH = 16, //Width the "byte" enable controls
+        parameter DATA_WIDTH = COL_WIDTH*NUM_COL, //Do not set this to anything else
+        parameter PIPELINE_DEPTH = 1, //Depth of the output pipeline, is latency in clock cycles
+        parameter CASCADE_DEPTH = 4 //Maximum depth of the memory block cascade
+    )
+    (
+        input logic clk,
+        //Port A
+        input logic a_en,
+        input logic[NUM_COL-1:0] a_wbe,
+        input logic[DATA_WIDTH-1:0] a_wdata,
+        input logic[ADDR_WIDTH-1:0] a_addr,
+
+        //Port B
+        input logic b_en,
+        input logic[ADDR_WIDTH-1:0] b_addr,
+        output logic[DATA_WIDTH-1:0] b_rdata
+    );
+
+    //Pad columns to the nearest multiple of 8 or 9 to allow the use of the byte enable
+    //This results in a more compact BRAM encoding
+    localparam PAD_WIDTH8 = (8 - (COL_WIDTH % 8)) % 8;
+    localparam PAD_WIDTH9 = (9 - (COL_WIDTH % 9)) % 9;
+    localparam PAD_WIDTH = PAD_WIDTH8 <= PAD_WIDTH9 ? PAD_WIDTH8 : PAD_WIDTH9;
+    localparam PADDED_WIDTH = COL_WIDTH + PAD_WIDTH;
+    localparam TOTAL_WIDTH = NUM_COL * PADDED_WIDTH;
+
+    generate if (PAD_WIDTH == 0 || NUM_COL == 1) begin : gen_no_padding
+        sdp_ram #(
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .NUM_COL(NUM_COL),
+            .COL_WIDTH(COL_WIDTH),
+            .PIPELINE_DEPTH(PIPELINE_DEPTH),
+            .CASCADE_DEPTH(CASCADE_DEPTH)
+        ) mem (.*);
+    end else begin : gen_padded
+        logic[TOTAL_WIDTH-1:0] a_padded;
+        logic[TOTAL_WIDTH-1:0] b_padded;
+
+        always_comb begin
+            a_padded = 'x;
+            for (int i = 0; i < NUM_COL; i++) begin
+                a_padded[i*PADDED_WIDTH+:COL_WIDTH] = a_wdata[i*COL_WIDTH+:COL_WIDTH];
+                b_rdata[i*COL_WIDTH+:COL_WIDTH] = b_padded[i*PADDED_WIDTH+:COL_WIDTH];
+            end
+        end
+
+        sdp_ram #(
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .NUM_COL(NUM_COL),
+            .COL_WIDTH(PADDED_WIDTH),
+            .PIPELINE_DEPTH(PIPELINE_DEPTH),
+            .CASCADE_DEPTH(CASCADE_DEPTH)
+        ) mem (
+            .a_wdata(a_padded),
+            .b_rdata(b_padded),
+        .*);
+    end endgenerate
+
+endmodule

core/common_components/toggle_memory.sv

@@ -22,16 +22,12 @@
 
 module toggle_memory
 
-    import cva5_config::*;
-    import cva5_types::*;
-
     # (
         parameter DEPTH = 8,
         parameter NUM_READ_PORTS = 2
     )
     (
         input logic clk,
-        input logic rst,
 
         input logic toggle,
         input logic [$clog2(DEPTH)-1:0] toggle_id,