Upstream bender changes (#1493)

* [bender] Fix bender scipt Signed-off-by: Florian Zaruba <[email protected]> * [bender] Remove standard `acc_dispatcher` Signed-off-by: Florian Zaruba <[email protected]> --------- Signed-off-by: Florian Zaruba <[email protected]>
openhwgroup · Oct 2, 2023 · 1726599 · 1726599
1 parent 20dec24
commit 1726599
Showing 1 changed file with 11 additions and 10 deletions.
diff --git a/Bender.yml b/Bender.yml
@@ -21,6 +21,8 @@ frozen: true
 
 sources:
   - files:
+      - core/include/config_pkg.sv
+
       - target: cv64a6_imafdcv_sv39
         files:
           - core/include/cv64a6_imafdcv_sv39_config_pkg.sv
@@ -81,12 +83,6 @@ sources:
       - core/include/acc_pkg.sv
 
       # for all the below files use Flist.cva6 as baseline and also look at Makefile pd/synth
-
-      # FPGA support keep vendoring here because too old
-      - vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv
-      - vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv
-      - vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv
-
       # CVXIF
       - core/include/instr_tracer_pkg.sv
       - core/include/cvxif_pkg.sv
@@ -133,7 +129,6 @@ sources:
       #     - vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
 
       # Top-level source files (not necessarily instantiated at the top of the cva6).
-      - corev_apu/src/ariane.sv
       - core/cva6.sv
       - core/alu.sv
       # Note: depends on fpnew_pkg, above
@@ -148,7 +143,6 @@ sources:
       - core/instr_realign.sv
       - core/id_stage.sv
       - core/issue_read_operands.sv
-      - core/acc_dispatcher.sv
       - core/issue_stage.sv
       - core/load_unit.sv
       - core/load_store_unit.sv
@@ -185,6 +179,13 @@ sources:
       - core/cache_subsystem/cva6_icache.sv
       - core/cache_subsystem/wt_cache_subsystem.sv
       - core/cache_subsystem/wt_axi_adapter.sv
+      - core/cache_subsystem/tag_cmp.sv
+      - core/cache_subsystem/cva6_icache_axi_wrapper.sv
+      - core/cache_subsystem/axi_adapter.sv
+      - core/cache_subsystem/miss_handler.sv
+      - core/cache_subsystem/cache_ctrl.sv
+      - core/cache_subsystem/std_nbdcache.sv
+      - core/cache_subsystem/std_cache_subsystem.sv
 
       # Physical Memory Protection
       # NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
@@ -212,12 +213,12 @@ sources:
       - target: not(synthesis)
         include_dirs:
           - core/include
+          - common/local/util
         files:
           # Tracer (behavioral code, not RTL)
+          - core/include/instr_tracer_pkg.sv
           - common/local/util/instr_tracer.sv
           - common/local/util/instr_tracer_if.sv
-          - common/local/util/instr_trace_item.svh
-          - common/local/util/ex_trace_item.svh
 
     # TODO target define FPGA target + verification etc
     #   - target: test