Re-factor halt and exception address as parameter

openhwgroup · Sep 11, 2023 · 18099f6 · 18099f6
1 parent 62e894d
commit 18099f6
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Showing 12 changed files with 48 additions and 70 deletions.
diff --git a/Bender.yml b/Bender.yml
@@ -25,7 +25,6 @@ sources:
         files:
           - core/include/cv64a6_imafdcv_sv39_config_pkg.sv
           - core/include/riscv_pkg.sv
-          - core/include/ariane_dm_pkg.sv
           - core/include/ariane_pkg.sv
           - core/mmu_sv39/tlb.sv
           - core/mmu_sv39/mmu.sv
@@ -36,7 +35,6 @@ sources:
         files:
           - core/include/cv64a6_imafdc_sv39_config_pkg.sv
           - core/include/riscv_pkg.sv
-          - core/include/ariane_dm_pkg.sv
           - core/include/ariane_pkg.sv
           - core/mmu_sv39/tlb.sv
           - core/mmu_sv39/mmu.sv
@@ -47,7 +45,6 @@ sources:
         files:
           - core/include/cv32a6_imac_sv0_config_pkg.sv
           - core/include/riscv_pkg.sv
-          - core/include/ariane_dm_pkg.sv
           - core/include/ariane_pkg.sv
           - core/mmu_sv32/cva6_tlb_sv32.sv
           - core/mmu_sv32/cva6_mmu_sv32.sv
@@ -58,7 +55,6 @@ sources:
         files:
           - core/include/cv32a6_imac_sv32_config_pkg.sv
           - core/include/riscv_pkg.sv
-          - core/include/ariane_dm_pkg.sv
           - core/include/ariane_pkg.sv
           - core/mmu_sv32/cva6_tlb_sv32.sv
           - core/mmu_sv32/cva6_mmu_sv32.sv
@@ -69,7 +65,6 @@ sources:
         files:
           - core/include/cv32a6_imafc_sv32_config_pkg.sv
           - core/include/riscv_pkg.sv
-          - core/include/ariane_dm_pkg.sv
           - core/include/ariane_pkg.sv
           - core/mmu_sv32/cva6_tlb_sv32.sv
           - core/mmu_sv32/cva6_mmu_sv32.sv

diff --git a/Flist.ariane b/Flist.ariane
@@ -21,7 +21,6 @@
 
 core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
 core/include/riscv_pkg.sv
-core/include/ariane_dm_pkg.sv
 common/local/rvfi/rvfi_pkg.sv
 core/include/ariane_pkg.sv
 corev_apu/tb/ariane_soc_pkg.sv

diff --git a/core/Flist.cva6 b/core/Flist.cva6
@@ -57,7 +57,6 @@ ${CVA6_REPO_DIR}/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mv
 
 ${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
 ${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
-${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
 // Note: depends on fpnew_pkg, above
 ${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv

diff --git a/core/Flist.cva6_gate b/core/Flist.cva6_gate
@@ -10,7 +10,6 @@
 
 ${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
 ${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
-${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
 ${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv
 

diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
@@ -1018,7 +1018,7 @@ module csr_regfile import ariane_pkg::*; #(
                 endcase
                 // save PC of next this instruction e.g.: the next one to be executed
                 dpc_d = {{riscv::XLEN-riscv::VLEN{pc_i[riscv::VLEN-1]}},pc_i};
-                dcsr_d.cause = ariane_dm_pkg::CauseBreakpoint;
+                dcsr_d.cause = ariane_pkg::CauseBreakpoint;
             end
 
             // we've got a debug request
@@ -1031,7 +1031,7 @@ module csr_regfile import ariane_pkg::*; #(
                 // jump to the base address
                 set_debug_pc_o = 1'b1;
                 // save the cause as external debug request
-                dcsr_d.cause = ariane_dm_pkg::CauseRequest;
+                dcsr_d.cause = ariane_pkg::CauseRequest;
             end
 
             // single step enable and we just retired an instruction
@@ -1053,7 +1053,7 @@ module csr_regfile import ariane_pkg::*; #(
                 end
                 debug_mode_d = 1'b1;
                 set_debug_pc_o = 1'b1;
-                dcsr_d.cause = ariane_dm_pkg::CauseSingleStep;
+                dcsr_d.cause = ariane_pkg::CauseSingleStep;
             end
         end
         // go in halt-state again when we encounter an exception
@@ -1250,7 +1250,7 @@ module csr_regfile import ariane_pkg::*; #(
 
         // if we are in debug mode jump to a specific address
         if (debug_mode_q) begin
-            trap_vector_base_o = DmBaseAddress[riscv::VLEN-1:0] + ariane_dm_pkg::ExceptionAddress[riscv::VLEN-1:0];
+            trap_vector_base_o = DmBaseAddress[riscv::VLEN-1:0] + CVA6Cfg.ExceptionAddress[riscv::VLEN-1:0];
         end
 
         // check if we are in vectored mode, if yes then do BASE + 4 * cause we

diff --git a/core/cva6.sv b/core/cva6.sv
@@ -20,7 +20,9 @@ module cva6 import ariane_pkg::*; #(
     unsigned'(cva6_config_pkg::CVA6ConfigAxiAddrWidth),   // AxiAddrWidth
     unsigned'(cva6_config_pkg::CVA6ConfigAxiDataWidth),   // AxiDataWidth
     unsigned'(cva6_config_pkg::CVA6ConfigAxiIdWidth),     // AxiIdWidth
-    unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth)   // AxiUserWidth
+    unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth),  // AxiUserWidth
+    64'h0, // HaltAddress
+    64'h0  // ExceptionAddress
   },
   parameter type rvfi_instr_t = struct packed {
     logic [ariane_pkg::NRET-1:0]                  valid;
@@ -693,8 +695,8 @@ module cva6 import ariane_pkg::*; #(
   csr_regfile #(
     .CVA6Cfg                ( CVA6Cfg                       ),
     .AsidWidth              ( ASID_WIDTH                    ),
-    .DmBaseAddress          ( ArianeCfg.DmBaseAddress       ),
     .NrPMPEntries           ( ArianeCfg.NrPMPEntries        ),
+    .DmBaseAddress          ( ArianeCfg.DmBaseAddress       ),
     .MHPMCounterNum         ( MHPMCounterNum                )
   ) csr_regfile_i (
     .flush_o                ( flush_csr_ctrl                ),

diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv
@@ -350,7 +350,7 @@ module frontend import ariane_pkg::*; #(
       end
       // 7. Debug
       // enter debug on a hard-coded base-address
-      if (set_debug_pc_i) npc_d = ArianeCfg.DmBaseAddress[riscv::VLEN-1:0] + ariane_dm_pkg::HaltAddress[riscv::VLEN-1:0];
+      if (set_debug_pc_i) npc_d = ArianeCfg.DmBaseAddress[riscv::VLEN-1:0] + CVA6Cfg.HaltAddress[riscv::VLEN-1:0];
       icache_dreq_o.vaddr = fetch_address;
     end
 

diff --git a/core/include/ariane_dm_pkg.sv b/core/include/ariane_dm_pkg.sv
diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv
@@ -41,6 +41,10 @@ package ariane_pkg;
       int unsigned AxiDataWidth;
       int unsigned AxiIdWidth;
       int unsigned AxiUserWidth;
+      // Debug Module
+      // address to which a hart should jump when it was requested to halt
+      logic [63:0] HaltAddress;
+      logic [63:0] ExceptionAddress;
     } cva6_cfg_t;
 
     localparam cva6_cfg_t cva6_cfg_empty = {
@@ -49,7 +53,9 @@ package ariane_pkg;
       unsigned'(0),  // AxiAddrWidth
       unsigned'(0),  // AxiDataWidth
       unsigned'(0),  // AxiIdWidth
-      unsigned'(0)   // AxiUserWidth
+      unsigned'(0),  // AxiUserWidth
+      64'h0,         // HaltAddress
+      64'h0          // ExceptionAddress
     };
 
     localparam NrMaxRules = 16;
@@ -256,13 +262,33 @@ package ariane_pkg;
     typedef logic [(NR_RGPR_PORTS == 3 ? riscv::XLEN : FLEN)-1:0] rs3_len_t;
 
     // static debug hartinfo
-    localparam ariane_dm_pkg::hartinfo_t DebugHartInfo = '{
+    // debug causes
+    localparam logic [2:0] CauseBreakpoint = 3'h1;
+    localparam logic [2:0] CauseTrigger    = 3'h2;
+    localparam logic [2:0] CauseRequest    = 3'h3;
+    localparam logic [2:0] CauseSingleStep = 3'h4;
+    // amount of data count registers implemented
+    localparam logic [3:0] DataCount     = 4'h2;
+
+    // address where data0-15 is shadowed or if shadowed in a CSR
+    // address of the first CSR used for shadowing the data
+    localparam logic [11:0] DataAddr = 12'h380; // we are aligned with Rocket here
+    typedef struct packed {
+      logic [31:24] zero1;
+      logic [23:20] nscratch;
+      logic [19:17] zero0;
+      logic         dataaccess;
+      logic [15:12] datasize;
+      logic [11:0]  dataaddr;
+    } hartinfo_t;
+
+    localparam hartinfo_t DebugHartInfo = '{
                                                 zero1:        '0,
                                                 nscratch:      2, // Debug module needs at least two scratch regs
                                                 zero0:        '0,
                                                 dataaccess: 1'b1, // data registers are memory mapped in the debugger
-                                                datasize: ariane_dm_pkg::DataCount,
-                                                dataaddr: ariane_dm_pkg::DataAddr
+                                                datasize: DataCount,
+                                                dataaddr: DataAddr
                                               };
 
     // enables a commit log which matches spikes commit log format for easier trace comparison

diff --git a/corev_apu/fpga/src/ariane_xilinx.sv b/corev_apu/fpga/src/ariane_xilinx.sv
@@ -161,7 +161,9 @@ localparam ariane_pkg::cva6_cfg_t CVA6Cfg = {
   unsigned'(cva6_config_pkg::CVA6ConfigAxiAddrWidth),   // AxiAddrWidth
   unsigned'(cva6_config_pkg::CVA6ConfigAxiDataWidth),   // AxiDataWidth
   unsigned'(cva6_config_pkg::CVA6ConfigAxiIdWidth),     // AxiIdWidth
-  unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth)   // DataUserWidth
+  unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth),  // DataUserWidth
+  dm::HaltAddress,
+  dm::ExceptionAddress
 };
 localparam type rvfi_instr_t = logic;
 

diff --git a/corev_apu/tb/ariane_tb.sv b/corev_apu/tb/ariane_tb.sv
@@ -35,7 +35,9 @@ module ariane_tb;
         unsigned'(cva6_config_pkg::CVA6ConfigAxiAddrWidth),   // AxiAddrWidth
         unsigned'(cva6_config_pkg::CVA6ConfigAxiDataWidth),   // AxiDataWidth
         unsigned'(cva6_config_pkg::CVA6ConfigAxiIdWidth),     // AxiIdWidth
-        unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth)   // AxiUserWidth
+        unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth),  // AxiUserWidth
+        dm::HaltAddress,
+        dm::ExceptionAddress
     };
     localparam type rvfi_instr_t = struct packed {
         logic [ariane_pkg::NRET-1:0]                  valid;

diff --git a/corev_apu/tb/ariane_testharness.sv b/corev_apu/tb/ariane_testharness.sv
@@ -22,7 +22,9 @@ module ariane_testharness #(
     unsigned'(cva6_config_pkg::CVA6ConfigAxiAddrWidth),   // AxiAddrWidth
     unsigned'(cva6_config_pkg::CVA6ConfigAxiDataWidth),   // AxiDataWidth
     unsigned'(cva6_config_pkg::CVA6ConfigAxiIdWidth),     // AxiIdWidth
-    unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth)   // AxiUserWidth
+    unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth),  // AxiUserWidth
+    dm::HaltAddress,
+    dm::ExceptionAddress
   },
   parameter type rvfi_instr_t = struct packed {
     logic [ariane_pkg::NRET-1:0]                  valid;