Merge branch 'master' into fix_BHT_fpga_optimization

openhwgroup · Oct 16, 2024 · 2063da7 · 2063da7
2 parents d3a4f40 + dff6271
commit 2063da7
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Showing 5 changed files with 41 additions and 27 deletions.
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -272,7 +272,7 @@ asic-synthesis:
     - echo $PERIOD
     - echo $DV_TARGET
     - source ./verif/sim/setup-env.sh
-    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH}
+    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH}
     - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
     - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
     - echo $SYN_DCSHELL_BASHRC; source $SYN_DCSHELL_BASHRC
@@ -526,19 +526,21 @@ simu-gate:
     matrix:
       - SIMU_PERIOD: ["20"]  # 50 Mhz
         PERIOD:      ["15"]  # 66 Mhz
+        PROG_NAME:   "dhrystone"
   variables:
     DASHBOARD_JOB_TITLE: "Gate Level Simulation $DV_TARGET"
     DASHBOARD_JOB_DESCRIPTION: "Tests to check netlist from ASIC synthesis and power consumption over different patterns"
     DASHBOARD_SORT_INDEX: 6
     DASHBOARD_JOB_CATEGORY: "Post Synthesis"
     DV_TARGET: cv32a65x
     TARGET: $DV_TARGET
+    SPIKE_TANDEM: 1
   script:
     - git -C verif/core-v-verif fetch --unshallow
     - !reference [.copy_spike_artifacts]
     - echo $PERIOD
     - source ./verif/sim/setup-env.sh
-    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH}
+    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH}
     - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
     - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
     - source verif/regress/install-riscv-tests.sh
@@ -548,6 +550,7 @@ simu-gate:
     - mkdir -p pd/synth/cva6_${DV_TARGET}/outputs/
     - python3 ${SYNTH_SCRIPT_PATH}/scharm -p configs/modules/CVA6.yml --runner=True --compaign="simu-gate" --name=$PROG_NAME
     - mv ${SYNTH_SCRIPT_PATH}/artifacts/ artifacts/artifacts_gate/
+    - rm artifacts/artifacts_gate/*/build/*.fsdb
   after_script: *simu_after_script
 
 fpga-boot:

diff --git a/.gitlab-ci/expected_synth.yml b/.gitlab-ci/expected_synth.yml
@@ -1,2 +1,2 @@
 cv32a65x:
-  gates: 171804
+  gates: 176232
diff --git a/core/cva6.sv b/core/cva6.sv
@@ -27,7 +27,7 @@ module cva6
     parameter type rvfi_probes_instr_t = `RVFI_PROBES_INSTR_T(CVA6Cfg),
     parameter type rvfi_probes_csr_t = `RVFI_PROBES_CSR_T(CVA6Cfg),
     parameter type rvfi_probes_t = struct packed {
-      logic csr;
+      rvfi_probes_csr_t   csr;
       rvfi_probes_instr_t instr;
     },
 

diff --git a/verif/tb/uvmt/uvmt_cva6_axi_assert.sv b/verif/tb/uvmt/uvmt_cva6_axi_assert.sv
@@ -18,42 +18,42 @@ module  uvmt_cva6_axi_assert#(int HPDCache=2)
 
    //check if the CVA6 identify read transaction with an ID equal to 0 or 1
    property AXI4_CVA6_ARID;
-      @(posedge axi_assert_if.clk && (HPDCache != 2)) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_id == 0 || axi_assert_if.ar_id == 1 || (axi_assert_if.ar_id == 3 && axi_assert_if.ar_lock == 1);
+      @(posedge axi_assert_if.clk && (HPDCache != 2) && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_id == 0 || axi_assert_if.ar_id == 1 || (axi_assert_if.ar_id == 3 && axi_assert_if.ar_lock == 1);
    endproperty
 
    //check if the CVA6 identify write transaction with an ID equal to 0 or 1
    property AXI4_CVA6_AWID;
-      @(posedge axi_assert_if.clk && (HPDCache != 2)) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_id == 1 || (axi_assert_if.aw_id == 3 && axi_assert_if.aw_atop != 0) || (axi_assert_if.aw_id == 3 && axi_assert_if.aw_lock == 1);
+      @(posedge axi_assert_if.clk && (HPDCache != 2) && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_id == 1 || (axi_assert_if.aw_id == 3 && axi_assert_if.aw_atop != 0) || (axi_assert_if.aw_id == 3 && axi_assert_if.aw_lock == 1);
    endproperty
 
    //Check if user-defined extension for read address channel is equal to 0b00
    property AXI4_CVA6_ARUSER;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_user == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_user == 0;
    endproperty
 
    //Check if user-defined extension for write address channel is equal to 0b00
    property AXI4_CVA6_AWUSER;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_user == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_user == 0;
    endproperty
 
    //Check if Quality of Service identifier for write transaction is equal to 0b0000
    property AXI4_CVA6_AWQOS;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_qos == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_qos == 0;
    endproperty
 
    //Check if Quality of Service identifier for read transaction is equal to 0b0000
    property AXI4_CVA6_ARQOS;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_qos == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_qos == 0;
    endproperty
 
    //Check if Region indicator for write transaction is equal to 0b0000
    property AXI4_CVA6_AWREGION;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_region == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_region == 0;
    endproperty
 
    //Check if Region indicator for read transaction is equal to 0b0000
    property AXI4_CVA6_ARREGION;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_region == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_region == 0;
    endproperty
 
    //Check if AWCACHE is always equal to 0b0000
@@ -63,42 +63,42 @@ module  uvmt_cva6_axi_assert#(int HPDCache=2)
 
    //Check if ARCACHE is always equal to 0b0000
    property AXI4_CVA6_ARCACHE;
-      @(posedge axi_assert_if.clk && (HPDCache != 2)) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_cache == 2;
+      @(posedge axi_assert_if.clk && (HPDCache != 2) && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_cache == 2;
    endproperty
 
    //Check if Protection attributes for write transaction always take the 0b000
    property AXI4_CVA6_AWPROT;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_prot == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_prot == 0;
    endproperty
 
    //Check if Protection attributes for read transaction always take the 0b000
    property AXI4_CVA6_ARPROT;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_prot == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_prot == 0;
    endproperty
 
    //Check if all write transaction performed by CVA6 are of type INCR
    property AXI4_CVA6_AWBURST;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_burst == 1;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_burst == 1;
    endproperty
 
    //Check if all read transaction performed by CVA6 are of type INCR
    property AXI4_CVA6_ARBURST;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_burst == 1;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_burst == 1;
    endproperty
 
    //Check if all write transaction performed by CVA6 are equal to 0
    property AXI4_CVA6_AWLEN;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_len == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_len == 0;
    endproperty
 
    //Check if all Read transaction performed by CVA6 are equal to 0 or 1
    property AXI4_CVA6_ARLEN;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_len == 0 || axi_assert_if.ar_len == 1;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_len == 0 || axi_assert_if.ar_len == 1;
    endproperty
 
    //Check if all Write transaction performed by CVA6 are of type Non atomic, AtomicLoad or AtomicSwap
    property AXI4_CVA6_AWATOP;
-      @(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> (axi_assert_if.aw_atop[5:4] == 0 || axi_assert_if.aw_atop[5:4] == 2 || axi_assert_if.aw_atop[5:4] == 3) && axi_assert_if.aw_atop[3] == 0;
+      @(posedge axi_assert_if.clk && axi_assert_if.axi_assertion_enabled) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> (axi_assert_if.aw_atop[5:4] == 0 || axi_assert_if.aw_atop[5:4] == 2 || axi_assert_if.aw_atop[5:4] == 3) && axi_assert_if.aw_atop[3] == 0;
    endproperty
 
 /********************************************** Assert Property ******************************************************/

diff --git a/verif/tb/uvmt/uvmt_cva6_tb.sv b/verif/tb/uvmt/uvmt_cva6_tb.sv
@@ -350,17 +350,28 @@ module uvmt_cva6_tb;
     * Test bench entry point.
     */
    initial begin : test_bench_entry_point
+     bit axi_assert_on;
 
      // Specify time format for simulation (units_number, precision_number, suffix_string, minimum_field_width)
      $timeformat(-9, 3, " ns", 8);
 
-     axi_if.aw_assertion_enabled      = 1;
-     axi_if.w_assertion_enabled       = 1;
-     axi_if.b_assertion_enabled       = 1;
-     axi_if.ar_assertion_enabled      = 1;
-     axi_if.r_assertion_enabled       = 1;
-     axi_if.axi_assertion_enabled     = 1;
-     axi_if.axi_amo_assertion_enabled = 1;
+     if($value$plusargs("uvmt_set_axi_assert_cfg=%0d", axi_assert_on)) begin
+        axi_if.aw_assertion_enabled      = axi_assert_on;
+        axi_if.w_assertion_enabled       = axi_assert_on;
+        axi_if.b_assertion_enabled       = axi_assert_on;
+        axi_if.ar_assertion_enabled      = axi_assert_on;
+        axi_if.r_assertion_enabled       = axi_assert_on;
+        axi_if.axi_assertion_enabled     = axi_assert_on;
+        axi_if.axi_amo_assertion_enabled = axi_assert_on;
+     end else begin
+        axi_if.aw_assertion_enabled      = 1;
+        axi_if.w_assertion_enabled       = 1;
+        axi_if.b_assertion_enabled       = 1;
+        axi_if.ar_assertion_enabled      = 1;
+        axi_if.r_assertion_enabled       = 1;
+        axi_if.axi_assertion_enabled     = 1;
+        axi_if.axi_amo_assertion_enabled = 1;
+     end
 
      // Add interfaces handles to uvm_config_db
      uvm_config_db#(virtual uvma_clknrst_if )::set(.cntxt(null), .inst_name("*.env.clknrst_agent"), .field_name("vif"),       .value(clknrst_if));