Define RVFI as cva6 parameter (#1293)

Bender.yml

@@ -25,7 +25,6 @@ sources:
         files:
           - core/include/cv64a6_imafdcv_sv39_config_pkg.sv
           - core/include/riscv_pkg.sv
-          - common/local/rvfi/rvfi_pkg.sv
           - core/include/ariane_dm_pkg.sv
           - core/include/ariane_pkg.sv
           - core/mmu_sv39/tlb.sv
@@ -37,7 +36,6 @@ sources:
         files:
           - core/include/cv64a6_imafdc_sv39_config_pkg.sv
           - core/include/riscv_pkg.sv
-          - common/local/rvfi/rvfi_pkg.sv
           - core/include/ariane_dm_pkg.sv
           - core/include/ariane_pkg.sv
           - core/mmu_sv39/tlb.sv
@@ -49,7 +47,6 @@ sources:
         files:
           - core/include/cv32a6_imac_sv0_config_pkg.sv
           - core/include/riscv_pkg.sv
-          - common/local/rvfi/rvfi_pkg.sv
           - core/include/ariane_dm_pkg.sv
           - core/include/ariane_pkg.sv
           - core/mmu_sv32/cva6_tlb_sv32.sv
@@ -61,7 +58,6 @@ sources:
         files:
           - core/include/cv32a6_imac_sv32_config_pkg.sv
           - core/include/riscv_pkg.sv
-          - common/local/rvfi/rvfi_pkg.sv
           - core/include/ariane_dm_pkg.sv
           - core/include/ariane_pkg.sv
           - core/mmu_sv32/cva6_tlb_sv32.sv

Makefile

@@ -525,7 +525,7 @@ xrun-ci: xrun-asm-tests xrun-amo-tests xrun-mul-tests xrun-fp-tests xrun-benchma
 verilate_command := $(verilator) verilator_config.vlt                                                            \
                     -f core/Flist.cva6                                                                           \
                     $(filter-out %.vhd, $(ariane_pkg))                                                           \
-                    $(filter-out core/fpu_wrap.sv, $(filter-out %.vhd, $(src)))                                  \
+                    $(filter-out core/fpu_wrap.sv, $(filter-out %.vhd, $(filter-out %_config_pkg.sv, $(src))))    \
                     +define+$(defines)$(if $(TRACE_FAST),+VM_TRACE)$(if $(TRACE_COMPACT),+VM_TRACE+VM_TRACE_FST) \
                     corev_apu/tb/common/mock_uart.sv                                                             \
                     +incdir+corev_apu/axi_node                                                                   \

config_pkg_generator.py

@@ -154,7 +154,6 @@ def setup_parser_config_generator():
   "PerfCounterEn": "CVA6ConfigPerfCounterEn",
   "DcacheType": "CVA6ConfigDcacheType",
   "MmuPresent": "CVA6ConfigMmuPresent",
-  "RvfiTrace": "RVFI_PORT",
   # Ignored parameters
   "ignored": "CVA6ConfigRvfiTrace",
 }

core/Flist.cva6

@@ -57,7 +57,6 @@ ${CVA6_REPO_DIR}/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mv
 
 ${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
 ${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
-${CVA6_REPO_DIR}/common/local/rvfi/rvfi_pkg.sv
 ${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
 // Note: depends on fpnew_pkg, above
 ${CVA6_REPO_DIR}/core/include/ariane_pkg.sv

core/Flist.cva6_gate

@@ -10,7 +10,6 @@
 
 ${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
 ${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
-${CVA6_REPO_DIR}/common/local/rvfi/rvfi_pkg.sv
 ${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
 ${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
 // TODO: ariane_axi_pkg is dependent on this.

core/acc_dispatcher.sv

@@ -14,6 +14,7 @@
 // Description: Functional unit that dispatches CVA6 instructions to accelerators.
 
 module acc_dispatcher import ariane_pkg::*; import riscv::*; #(
+    parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
     parameter type acc_req_t  = acc_pkg::accelerator_req_t,
     parameter type acc_resp_t = acc_pkg::accelerator_resp_t
 ) (
@@ -31,15 +32,15 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; #(
     input  logic                                  issue_instr_hs_i,
     output logic                                  issue_stall_o,
     input  fu_data_t                              fu_data_i,
-    input  scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_i,
+    input  scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
     output logic              [TRANS_ID_BITS-1:0] acc_trans_id_o,
     output xlen_t                                 acc_result_o,
     output logic                                  acc_valid_o,
     output exception_t                            acc_exception_o,
     // Interface with the execute stage
     output logic                                  acc_valid_ex_o,       // FU executed
     // Interface with the commit stage
-    input  logic            [NR_COMMIT_PORTS-1:0] commit_ack_i,
+    input  logic      [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
     input  logic                                  commit_st_barrier_i,  // A store barrier was commited
     // Interface with the load/store unit
     input  logic                                  acc_no_st_pending_i,
@@ -286,7 +287,7 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; #(
   // Dirty the V state if we are committing anything related to the vector accelerator
   always_comb begin : dirty_v_state
     dirty_v_state_o = 1'b0;
-    for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
+    for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
       dirty_v_state_o |= commit_ack_i[i] & (commit_instr_i[i].fu == ACCEL);
     end
   end

core/alu.sv

@@ -19,7 +19,7 @@
 
 
 module alu import ariane_pkg::*; #(
-    parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
+    parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
 ) (
     input  logic                     clk_i,          // Clock
     input  logic                     rst_ni,         // Asynchronous reset active low

core/amo_buffer.sv

@@ -15,7 +15,7 @@
 // Furthermore it handles interfacing with the commit stage
 
 module amo_buffer #(
-    parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
+    parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
 ) (
     input  logic clk_i,              // Clock
     input  logic rst_ni,             // Asynchronous reset active low

core/ariane_regfile.sv

@@ -24,10 +24,9 @@
 //
 
 module ariane_regfile_lol #(
-  parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
+  parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
   parameter int unsigned DATA_WIDTH     = 32,
   parameter int unsigned NR_READ_PORTS  = 2,
-  parameter int unsigned NR_WRITE_PORTS = 2,
   parameter bit          ZERO_REG_ZERO  = 0
 )(
   // clock and reset
@@ -39,9 +38,9 @@ module ariane_regfile_lol #(
   input  logic [NR_READ_PORTS-1:0][4:0]             raddr_i,
   output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0]  rdata_o,
   // write port
-  input  logic [NR_WRITE_PORTS-1:0][4:0]            waddr_i,
-  input  logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_i,
-  input  logic [NR_WRITE_PORTS-1:0]                 we_i
+  input  logic [CVA6Cfg.NrCommitPorts-1:0][4:0]            waddr_i,
+  input  logic [CVA6Cfg.NrCommitPorts-1:0][DATA_WIDTH-1:0] wdata_i,
+  input  logic [CVA6Cfg.NrCommitPorts-1:0]                 we_i
 );
 
     localparam ADDR_WIDTH = 5;
@@ -50,8 +49,8 @@ module ariane_regfile_lol #(
     logic [NUM_WORDS-1:ZERO_REG_ZERO]          mem_clocks;
 
     logic [DATA_WIDTH-1:0]                     mem[NUM_WORDS];
-    logic [NR_WRITE_PORTS-1:0][NUM_WORDS-1:1]  waddr_onehot,waddr_onehot_q;
-    logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_q;
+    logic [CVA6Cfg.NrCommitPorts-1:0][NUM_WORDS-1:1]  waddr_onehot,waddr_onehot_q;
+    logic [CVA6Cfg.NrCommitPorts-1:0][DATA_WIDTH-1:0] wdata_q;
 
 
     // decode addresses
@@ -62,7 +61,7 @@ module ariane_regfile_lol #(
         if (~rst_ni) begin
             wdata_q <= '0;
         end else begin
-            for (int unsigned i = 0; i < NR_WRITE_PORTS; i++)
+            for (int unsigned i = 0; i < CVA6Cfg.NrCommitPorts; i++)
                 // enable flipflop will most probably infer clock gating
                 if (we_i[i]) begin
                     wdata_q[i]     <= wdata_i[i];
@@ -73,7 +72,7 @@ module ariane_regfile_lol #(
 
     // WRITE : Write Address Decoder (WAD), combinatorial process
     always_comb begin : decode_write_addess
-        for (int unsigned i = 0; i < NR_WRITE_PORTS; i++) begin
+        for (int unsigned i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
             for (int unsigned j = 1; j < NUM_WORDS; j++) begin
                 if (we_i[i] && (waddr_i[i] == j))
                     waddr_onehot[i][j] = 1'b1;
@@ -86,9 +85,9 @@ module ariane_regfile_lol #(
     // WRITE : Clock gating (if integrated clock-gating cells are available)
     for (genvar x = ZERO_REG_ZERO; x < NUM_WORDS; x++) begin
 
-        logic [NR_WRITE_PORTS-1:0] waddr_ored;
+        logic [CVA6Cfg.NrCommitPorts-1:0] waddr_ored;
 
-        for (genvar i = 0; i < NR_WRITE_PORTS; i++)
+        for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++)
           assign waddr_ored[i] = waddr_onehot[i][x];
 
         cluster_clock_gating i_cg (
@@ -111,7 +110,7 @@ module ariane_regfile_lol #(
         if (ZERO_REG_ZERO)
             mem[0] = '0;
 
-        for (int unsigned i = 0; i < NR_WRITE_PORTS; i++) begin
+        for (int unsigned i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
             for (int unsigned k = ZERO_REG_ZERO; k < NUM_WORDS; k++) begin
                 if (mem_clocks[k] && waddr_onehot_q[i][k])
                     mem[k] = wdata_q[i];

core/ariane_regfile_ff.sv

@@ -23,10 +23,9 @@
 //
 
 module ariane_regfile #(
-  parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
+  parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
   parameter int unsigned DATA_WIDTH     = 32,
   parameter int unsigned NR_READ_PORTS  = 2,
-  parameter int unsigned NR_WRITE_PORTS = 2,
   parameter bit          ZERO_REG_ZERO  = 0
 )(
   // clock and reset
@@ -38,20 +37,20 @@ module ariane_regfile #(
   input  logic [NR_READ_PORTS-1:0][4:0]             raddr_i,
   output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0]  rdata_o,
   // write port
-  input  logic [NR_WRITE_PORTS-1:0][4:0]            waddr_i,
-  input  logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_i,
-  input  logic [NR_WRITE_PORTS-1:0]                 we_i
+  input  logic [CVA6Cfg.NrCommitPorts-1:0][4:0]            waddr_i,
+  input  logic [CVA6Cfg.NrCommitPorts-1:0][DATA_WIDTH-1:0] wdata_i,
+  input  logic [CVA6Cfg.NrCommitPorts-1:0]                 we_i
 );
 
   localparam    ADDR_WIDTH = 5;
   localparam    NUM_WORDS  = 2**ADDR_WIDTH;
 
   logic [NUM_WORDS-1:0][DATA_WIDTH-1:0]     mem;
-  logic [NR_WRITE_PORTS-1:0][NUM_WORDS-1:0] we_dec;
+  logic [CVA6Cfg.NrCommitPorts-1:0][NUM_WORDS-1:0] we_dec;
 
 
     always_comb begin : we_decoder
-        for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin
+        for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin
             for (int unsigned i = 0; i < NUM_WORDS; i++) begin
                 if (waddr_i[j] == i)
                     we_dec[j][i] = we_i[j];
@@ -66,7 +65,7 @@ module ariane_regfile #(
         if (~rst_ni) begin
             mem <= '{default: '0};
         end else begin
-            for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin
+            for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin
                 for (int unsigned i = 0; i < NUM_WORDS; i++) begin
                     if (we_dec[j][i]) begin
                         mem[i] <= wdata_i[j];

core/ariane_regfile_fpga.sv

@@ -26,10 +26,9 @@
 //
 
 module ariane_regfile_fpga #(
-  parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
+  parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
   parameter int unsigned DATA_WIDTH     = 32,
   parameter int unsigned NR_READ_PORTS  = 2,
-  parameter int unsigned NR_WRITE_PORTS = 2,
   parameter bit          ZERO_REG_ZERO  = 0
 )(
   // clock and reset
@@ -41,25 +40,25 @@ module ariane_regfile_fpga #(
   input  logic [NR_READ_PORTS-1:0][4:0]             raddr_i,
   output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0]  rdata_o,
   // write port
-  input  logic [NR_WRITE_PORTS-1:0][4:0]            waddr_i,
-  input  logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_i,
-  input  logic [NR_WRITE_PORTS-1:0]                 we_i
+  input  logic [CVA6Cfg.NrCommitPorts-1:0][4:0]            waddr_i,
+  input  logic [CVA6Cfg.NrCommitPorts-1:0][DATA_WIDTH-1:0] wdata_i,
+  input  logic [CVA6Cfg.NrCommitPorts-1:0]                 we_i
 );
 
   localparam ADDR_WIDTH = 5;
   localparam NUM_WORDS  = 2**ADDR_WIDTH;
-  localparam LOG_NR_WRITE_PORTS = NR_WRITE_PORTS == 1 ? 1 : $clog2(NR_WRITE_PORTS);
+  localparam LOG_NR_WRITE_PORTS = CVA6Cfg.NrCommitPorts == 1 ? 1 : $clog2(CVA6Cfg.NrCommitPorts);
 
   // Distributed RAM usually supports one write port per block - duplicate for each write port.
-  logic [NUM_WORDS-1:0][DATA_WIDTH-1:0]     mem [NR_WRITE_PORTS];
+  logic [NUM_WORDS-1:0][DATA_WIDTH-1:0]     mem [CVA6Cfg.NrCommitPorts];
 
-  logic [NR_WRITE_PORTS-1:0][NUM_WORDS-1:0]     we_dec;
+  logic [CVA6Cfg.NrCommitPorts-1:0][NUM_WORDS-1:0]     we_dec;
   logic [NUM_WORDS-1:0][LOG_NR_WRITE_PORTS-1:0] mem_block_sel;
   logic [NUM_WORDS-1:0][LOG_NR_WRITE_PORTS-1:0] mem_block_sel_q;
 
   // write adress decoder (for block selector)
   always_comb begin
-    for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin
+    for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin
       for (int unsigned i = 0; i < NUM_WORDS; i++) begin
         if (waddr_i[j] == i) begin
           we_dec[j][i] = we_i[j];
@@ -77,7 +76,7 @@ module ariane_regfile_fpga #(
   always_comb begin
     mem_block_sel = mem_block_sel_q;
     for (int i = 0; i<NUM_WORDS; i++) begin
-      for (int j = 0; j<NR_WRITE_PORTS; j++) begin
+      for (int j = 0; j<CVA6Cfg.NrCommitPorts; j++) begin
         if (we_dec[j][i] == 1'b1) begin
           mem_block_sel[i] = LOG_NR_WRITE_PORTS'(j);
         end
@@ -95,8 +94,8 @@ module ariane_regfile_fpga #(
   end
 
   // distributed RAM blocks
-  logic [NR_READ_PORTS-1:0] [DATA_WIDTH-1:0] mem_read [NR_WRITE_PORTS];
-  for (genvar j=0; j<NR_WRITE_PORTS; j++) begin : regfile_ram_block
+  logic [NR_READ_PORTS-1:0] [DATA_WIDTH-1:0] mem_read [CVA6Cfg.NrCommitPorts];
+  for (genvar j=0; j<CVA6Cfg.NrCommitPorts; j++) begin : regfile_ram_block
     always_ff @(posedge clk_i) begin
       if (we_i[j] && ~waddr_i[j] != 0) begin
         mem[j][waddr_i[j]] <= wdata_i[j];
@@ -118,7 +117,7 @@ module ariane_regfile_fpga #(
   // random initialization of the memory to suppress assert warnings on Questa.
   initial
   begin
-    for(int i = 0; i < NR_WRITE_PORTS; i++) begin
+    for(int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
       for(int j = 0; j < NUM_WORDS; j++) begin
         mem[i][j] = $random();
       end

core/axi_shim.sv

@@ -20,7 +20,7 @@
 
 
 module axi_shim #(
-  parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
+  parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
   parameter int unsigned AxiUserWidth = 64, // data width in dwords, this is also the maximum burst length, must be >=2
   parameter int unsigned AxiNumWords = 4, // data width in dwords, this is also the maximum burst length, must be >=2
   parameter int unsigned AxiAddrWidth = 0,

core/branch_unit.sv

@@ -13,7 +13,7 @@
 // Description: Branch target calculation and comparison
 
 module branch_unit #(
-    parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
+    parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
 ) (
     input  logic                      clk_i,
     input  logic                      rst_ni,

core/cache_subsystem/amo_alu.sv

@@ -12,7 +12,7 @@
 // Date: 15.09.2018
 // Description: Combinatorial AMO unit
 module amo_alu #(
-        parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
+        parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
 ) (
         // AMO interface
         input  ariane_pkg::amo_t  amo_op_i,

core/cache_subsystem/axi_adapter.sv

@@ -17,7 +17,7 @@
 //import std_cache_pkg::*;
 
 module axi_adapter #(
-  parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
+  parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
   parameter int unsigned DATA_WIDTH            = 256,
   parameter logic        CRITICAL_WORD_FIRST   = 0, // the AXI subsystem needs to support wrapping reads for this feature
   parameter int unsigned CACHELINE_BYTE_OFFSET = 8,