Add MSTATUSH register for RV32 (fix #1160)

openhwgroup · Aug 4, 2023 · 4de2026 · 4de2026
1 parent 853fb4b
commit 4de2026
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diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
@@ -241,6 +241,7 @@ module csr_regfile import ariane_pkg::*; #(
                 end
                 // machine mode registers
                 riscv::CSR_MSTATUS:            csr_rdata = mstatus_extended;
+                riscv::CSR_MSTATUSH:           if (riscv::XLEN == 32) csr_rdata = '0; else read_access_exception = 1'b1;
                 riscv::CSR_MISA:               csr_rdata = ISA_CODE;
                 riscv::CSR_MEDELEG:            csr_rdata = medeleg_q;
                 riscv::CSR_MIDELEG:            csr_rdata = mideleg_q;
@@ -684,6 +685,7 @@ module csr_regfile import ariane_pkg::*; #(
                     // this register has side-effects on other registers, flush the pipeline
                     flush_o        = 1'b1;
                 end
+                riscv::CSR_MSTATUSH: if (riscv::XLEN == 32) ; else update_access_exception = 1'b1;
                 // MISA is WARL (Write Any Value, Reads Legal Value)
                 riscv::CSR_MISA:;
                 // machine exception delegation register

diff --git a/core/include/riscv_pkg.sv b/core/include/riscv_pkg.sv
@@ -397,6 +397,7 @@ package riscv;
         CSR_MIE            = 12'h304,
         CSR_MTVEC          = 12'h305,
         CSR_MCOUNTEREN     = 12'h306,
+        CSR_MSTATUSH       = 12'h310,
         CSR_MCOUNTINHIBIT  = 12'h320,
         CSR_MHPM_EVENT_3   = 12'h323,  //Machine performance monitoring Event Selector
         CSR_MHPM_EVENT_4   = 12'h324,  //Machine performance monitoring Event Selector