Support multiple outstanding load operations to the Dcache

The ID in the request from the load/store unit must be mirrored by the
Dcache in the response. This allows to match a given response to its
corresponding request. Responses can be given (by the Dcache) in a
different order that the one of requests.

This modification introduces a pending load table that tracks
outstanding load operations to the Dcache. The depth of this table is
a parameter in the target configuration package.

Signed-off-by: Cesar Fuguet <[email protected]>

core/cache_subsystem/cache_ctrl.sv

@@ -74,6 +74,7 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
     typedef struct packed {
         logic [DCACHE_INDEX_WIDTH-1:0] index;
         logic [DCACHE_TAG_WIDTH-1:0]   tag;
+        logic [DCACHE_TID_WIDTH-1:0]   id;
         logic [7:0]             be;
         logic [1:0]             size;
         logic                   we;
@@ -116,7 +117,7 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
         req_port_o.data_gnt    = 1'b0;
         req_port_o.data_rvalid = 1'b0;
         req_port_o.data_rdata  = '0;
-        req_port_o.data_rid    = '0;
+        req_port_o.data_rid    = mem_req_q.id;
         miss_req_o    = '0;
         mshr_addr_o   = '0;
         // Memory array communication
@@ -138,6 +139,7 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
 
                     // save index, be and we
                     mem_req_d.index = req_port_i.address_index;
+                    mem_req_d.id    = req_port_i.data_id;
                     mem_req_d.be    = req_port_i.data_be;
                     mem_req_d.size  = req_port_i.data_size;
                     mem_req_d.we    = req_port_i.data_we;
@@ -186,6 +188,7 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
                         if (req_port_i.data_req && !mem_req_q.we && !flush_i) begin
                             state_d          = WAIT_TAG; // switch back to WAIT_TAG
                             mem_req_d.index  = req_port_i.address_index;
+                            mem_req_d.id     = req_port_i.data_id;
                             mem_req_d.be     = req_port_i.data_be;
                             mem_req_d.size   = req_port_i.data_size;
                             mem_req_d.we     = req_port_i.data_we;

core/cache_subsystem/wt_dcache_ctrl.sv

@@ -59,6 +59,7 @@ module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #(
   logic [DCACHE_TAG_WIDTH-1:0]    address_tag_d, address_tag_q;
   logic [DCACHE_CL_IDX_WIDTH-1:0] address_idx_d, address_idx_q;
   logic [DCACHE_OFFSET_WIDTH-1:0] address_off_d, address_off_q;
+  logic [DCACHE_TID_WIDTH-1:0]    id_d, id_q;
   logic [DCACHE_SET_ASSOC-1:0]    vld_data_d,    vld_data_q;
   logic save_tag, rd_req_d, rd_req_q, rd_ack_d, rd_ack_q;
   logic [1:0] data_size_d, data_size_q;
@@ -72,14 +73,15 @@ module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #(
   assign address_tag_d = (save_tag)            ? req_port_i.address_tag                                             : address_tag_q;
   assign address_idx_d = (req_port_o.data_gnt) ? req_port_i.address_index[DCACHE_INDEX_WIDTH-1:DCACHE_OFFSET_WIDTH] : address_idx_q;
   assign address_off_d = (req_port_o.data_gnt) ? req_port_i.address_index[DCACHE_OFFSET_WIDTH-1:0]                  : address_off_q;
+  assign id_d          = (req_port_o.data_gnt) ? req_port_i.data_id                                                 : id_q;
   assign data_size_d   = (req_port_o.data_gnt) ? req_port_i.data_size                                               : data_size_q;
   assign rd_tag_o      = address_tag_d;
   assign rd_idx_o      = address_idx_d;
   assign rd_off_o      = address_off_d;
 
   assign req_port_o.data_rdata = rd_data_i;
   assign req_port_o.data_ruser = rd_user_i;
-  assign req_port_o.data_rid   = '0;
+  assign req_port_o.data_rid   = id_q;
 
   // to miss unit
   assign miss_vld_bits_o       = vld_data_q;
@@ -240,6 +242,7 @@ module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #(
       address_tag_q    <= '0;
       address_idx_q    <= '0;
       address_off_q    <= '0;
+      id_q             <= '0;
       vld_data_q       <= '0;
       data_size_q      <= '0;
       rd_req_q         <= '0;
@@ -249,6 +252,7 @@ module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #(
       address_tag_q    <= address_tag_d;
       address_idx_q    <= address_idx_d;
       address_off_q    <= address_off_d;
+      id_q             <= id_d;
       vld_data_q       <= vld_data_d;
       data_size_q      <= data_size_d;
       rd_req_q         <= rd_req_d;

core/include/ariane_pkg.sv

@@ -667,6 +667,9 @@ package ariane_pkg;
         logic                       vfp;         // is this a vector floating-point instruction?
     } scoreboard_entry_t;
 
+    //  Maximum number of inflight memory load requests
+    localparam int unsigned NR_LOAD_BUFFER_ENTRIES = cva6_config_pkg::CVA6ConfigNrLoadBufEntries;
+
     // ---------------
     // MMU instanciation
     // ---------------

core/include/cv32a60x_config_pkg.sv

@@ -58,6 +58,7 @@ package cva6_config_pkg;
 
     localparam CVA6ConfigNrLoadPipeRegs = 1;
     localparam CVA6ConfigNrStorePipeRegs = 0;
+    localparam CVA6ConfigNrLoadBufEntries = 2;
 
     localparam CVA6ConfigInstrTlbEntries = 2;
     localparam CVA6ConfigDataTlbEntries = 2;

core/include/cv32a6_embedded_config_pkg.sv

@@ -57,6 +57,7 @@ package cva6_config_pkg;
 
     localparam CVA6ConfigNrLoadPipeRegs = 1;
     localparam CVA6ConfigNrStorePipeRegs = 0;
+    localparam CVA6ConfigNrLoadBufEntries = 2;
 
     localparam CVA6ConfigInstrTlbEntries = 2;
     localparam CVA6ConfigDataTlbEntries = 2;

core/include/cv32a6_ima_sv32_fpga_config_pkg.sv

@@ -58,6 +58,7 @@ package cva6_config_pkg;
 
     localparam CVA6ConfigNrLoadPipeRegs = 1;
     localparam CVA6ConfigNrStorePipeRegs = 0;
+    localparam CVA6ConfigNrLoadBufEntries = 2;
 
     localparam CVA6ConfigInstrTlbEntries = 2;
     localparam CVA6ConfigDataTlbEntries = 2;

core/include/cv32a6_imac_sv0_config_pkg.sv

@@ -53,6 +53,7 @@ package cva6_config_pkg;
 
     localparam CVA6ConfigNrCommitPorts = 2;
     localparam CVA6ConfigNrScoreboardEntries = 8;
+    localparam CVA6ConfigNrLoadBufEntries = 2;
 
     localparam CVA6ConfigFPGAEn = 0;
 

core/include/cv32a6_imac_sv32_config_pkg.sv

@@ -58,6 +58,7 @@ package cva6_config_pkg;
 
     localparam CVA6ConfigNrLoadPipeRegs = 1;
     localparam CVA6ConfigNrStorePipeRegs = 0;
+    localparam CVA6ConfigNrLoadBufEntries = 2;
 
     localparam CVA6ConfigInstrTlbEntries = 2;
     localparam CVA6ConfigDataTlbEntries = 2;

core/include/cv32a6_imafc_sv32_config_pkg.sv

@@ -58,6 +58,7 @@ package cva6_config_pkg;
 
     localparam CVA6ConfigNrLoadPipeRegs = 1;
     localparam CVA6ConfigNrStorePipeRegs = 0;
+    localparam CVA6ConfigNrLoadBufEntries = 2;
 
     localparam CVA6ConfigInstrTlbEntries = 2;
     localparam CVA6ConfigDataTlbEntries = 2;

core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv

@@ -58,6 +58,7 @@ package cva6_config_pkg;
 
     localparam CVA6ConfigNrLoadPipeRegs = 1;
     localparam CVA6ConfigNrStorePipeRegs = 0;
+    localparam CVA6ConfigNrLoadBufEntries = 2;
 
     localparam CVA6ConfigInstrTlbEntries = 16;
     localparam CVA6ConfigDataTlbEntries = 16;

core/include/cv64a6_imafdc_sv39_config_pkg.sv

@@ -58,6 +58,7 @@ package cva6_config_pkg;
 
     localparam CVA6ConfigNrLoadPipeRegs = 1;
     localparam CVA6ConfigNrStorePipeRegs = 0;
+    localparam CVA6ConfigNrLoadBufEntries = 2;
 
     localparam CVA6ConfigInstrTlbEntries = 16;
     localparam CVA6ConfigDataTlbEntries = 16;

core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv

@@ -58,6 +58,7 @@ package cva6_config_pkg;
 
     localparam CVA6ConfigNrLoadPipeRegs = 1;
     localparam CVA6ConfigNrStorePipeRegs = 0;
+    localparam CVA6ConfigNrLoadBufEntries = 2;
 
     localparam CVA6ConfigInstrTlbEntries = 16;
     localparam CVA6ConfigDataTlbEntries = 16;

core/include/cv64a6_imafdcv_sv39_config_pkg.sv

@@ -58,6 +58,7 @@ package cva6_config_pkg;
 
     localparam CVA6ConfigNrLoadPipeRegs = 1;
     localparam CVA6ConfigNrStorePipeRegs = 0;
+    localparam CVA6ConfigNrLoadBufEntries = 2;
 
     localparam CVA6ConfigInstrTlbEntries = 16;
     localparam CVA6ConfigDataTlbEntries = 16;