Traps_Interrupts_Exceptions.rst: update chapter #1291
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| On one hand, interrupts are occuring independently of the instructions | ||
| (mainly raised by peripherals or debug module). | ||
| On the other hand, an instruction may raise exceptions synchronously. | ||
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Suggest to mention that U-mode delegation of interrupts and exceptions is not supported.
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AFAIK, RISC-V privilege spec does not support (even optionally) U-mode delegation. So, I'm not sure it is useful to mention that in our manual.
Whatever, I add "S-mode" few lines below to precise what is the lower privilege mode.
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| CSRs having an effect on the core behaviour when a trap occurs are: | ||
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| * ``mstatus`` and ``sstatus``: several fields are read like interrupt enable (MIE, SIE) |
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I do not understand the context. Who / what entity reads?
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| * instruction access fault | ||
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| * physical address fault |
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Could you be more specific? E.g. error response from the memory bus.
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Rephrased with PMP permissions
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| * load access fault | ||
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| * access to PMP region without read permissions |
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What about write and execute permissions?
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For load, only read permissions
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| * store/AMO access fault | ||
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| * access to PMP region without write permissions |
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What about write and execute permissions?
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For store, only write permissions
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| Modified CSRs | ||
| ------------- | ||
| * ``mstatus``: several fields are updated like interrupt enable (MIE, SIE), modify privilege (MPRV) |
| ------------- | ||
| * ``mstatus``: several fields are updated like interrupt enable (MIE, SIE), modify privilege (MPRV) | ||
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| Interrupts |
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Could you add an introductory sentence, such as "These input signals of the CVA6 asynchronously trigger interrupts"?
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Interrupts are already introduced at the beginning of the chapter.
| * external interrupt: ``irq_i`` signal | ||
| * software interrupt (inter-processor interrupt): ``ipi_i`` signal | ||
| * timer interrupt: ``time_irq_i`` signal | ||
| * debug interrupt: ``debug_req_i`` signal |
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How can the programmer identify the source of the interrupt?
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Thanks to exception code field in mcause CSR. Added in the document.
| * timer interrupt: ``time_irq_i`` signal | ||
| * debug interrupt: ``debug_req_i`` signal | ||
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| These signals are level sensitive. |
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I understand this sentence. But is it clear for a programmer? May I suggest to add a second sentence: "The core will immediately interrupt again as long as the input signal stays in its active state"?
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| Wait for Interrupt | ||
| ================== | ||
| * CVA6 implementation: WFI stalls the core. The instruction is not available in U-mode (raise illegal instruction exception). Such exception is also raised when ``TW=1`` in ``mstatus``. |
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Very minor: add `` `` around WFI
Signed-off-by: André Sintzoff <[email protected]>
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