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Adding RISC-V behavior (WARL, WLRL, WPRI) to the specification of CSRs #1314

Merged

JeanRochCoulon merged 1 commit into openhwgroup:master from ThalesSiliconSecurity:addRISCVBehavior

Jul 20, 2023

Contributor

frikhaAziz commented Jul 20, 2023 •

edited by JeanRochCoulon

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Add WARL register access type to the specification
Will be useful to verify CSRs


          Adding RISC-V behavior (WARL, WLRL, WPRI) to the specification of CSRs

fc97c29

frikhaAziz requested a review from jquevremont as a code owner

July 20, 2023 16:53

JeanRochCoulon merged commit 716bc71 into openhwgroup:master

6 checks passed

JeanRochCoulon deleted the addRISCVBehavior branch

July 20, 2023 17:09

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