CV32A6 CSR Access Verification PR

verif/tests/custom/CSR/csr_access_failing_tests/README.md

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+This directory contain RISCV CVA6 CSR access mode failing tests.
+

verif/tests/custom/CSR/csr_access_failing_tests/riscv_marchid_csr_test_0.S

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+// Copyright 2023 Thales
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+#include "model_test.h"
+.macro init
+.endm
+.section .text.init
+.globl _start
+.option norvc
+.org 0x00
+_start:
+	la x6, exception_handler  
+        csrw mtvec, x6  ## Load the address of the exception handler into MTVEC
+	csrw 0x341, x0
+    	csrw 0x342, x0
+
+	# CSR_MARCHID
+	csrr x31, 3858
+	li x6, 0x00000003
+	bne x31, x4, csr_fail
+	li x4, 0xa5a5a5a5
+	csrrw x14, 3858, x4
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	li x4, 0x5a5a5a5a
+	csrrw x14, 3858, x4
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	li x4, 0x82cebeaf
+	csrrw x14, 3858, x4
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	li x4, 0xa5a5a5a5
+	csrrs x14, 3858, x4
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	li x4, 0x5a5a5a5a
+	csrrs x14, 3858, x4
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	li x4, 0xd6ecdb19
+	csrrs x14, 3858, x4
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	li x4, 0xa5a5a5a5
+	csrrc x14, 3858, x4
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	li x4, 0x5a5a5a5a
+	csrrc x14, 3858, x4
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	li x4, 0x6a7b6028
+	csrrc x14, 3858, x4
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	csrrwi x14, 3858, 0b00101
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	csrrwi x14, 3858, 0b11010
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	csrrwi x14, 3858, 0b01001
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	csrrsi x14, 3858, 0b00101
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	csrrsi x14, 3858, 0b11010
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	csrrsi x14, 3858, 0b01110
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	csrrci x14, 3858, 0b00101
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	csrrci x14, 3858, 0b11010
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	csrrci x14, 3858, 0b10110
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+	csrr x14, 3858
+	li x4, 0x00000003
+	bne x4, x14, csr_fail
+
+	j csr_pass
+
+exception_handler:
+csrr x30, 0x341	    ## Reading MEPC CSR which holds exception origin Address		
+csrr x31, 0x342     ## Reading MCAUSE CSR which holds the cause of exception
+addi x2, x2,2
+beq x31, x2, next   ## Checking is exception is expected exception or not
+j csr_fail
+
+next:
+addi x1, x1, 0
+bne x30, x1, next_iter  ## If MEPC has non-zero value then jump to next_iter
+j csr_fail
+
+next_iter:
+li x2, 0 		## Initilizing 0 in x2 register where MCAUSE value is previously stored
+addi x7, x30, 4
+jr x7			## Jump to MEPC + 4 Address location
+
+
+
+csr_pass:
+	li x1, 0
+	slli x1, x1, 1
+	addi x1, x1, 1
+	sw x1, tohost, t5
+	self_loop: j self_loop
+
+csr_fail:
+	li x1, 1
+	slli x1, x1, 1
+	addi x1, x1, 1
+	sw x1, tohost, t5
+	self_loop_2: j self_loop_2
+
+RVMODEL_DATA_BEGIN
+RVMODEL_DATA_END

verif/tests/custom/CSR/csr_access_failing_tests/riscv_mstatus_csr_test_0.S

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+// Copyright 2023 Thales
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+#include "model_test.h"
+.macro init
+.endm
+.section .text.init
+.globl _start
+.option norvc
+.org 0x00
+_start:
+RVMODEL_BOOT
+
+	# CSR_MSTATUS
+	li x6, 0xFFFFFFFF
+	csrrw x4, 768, x6
+	li x6, 0x00000000
+	bne x6, x4, csr_fail
+	li x6, 0x5a5a5a5a
+	csrrw x4, 768, x6
+	li x6, 0x8025a1a0
+	bne x6, x4, csr_fail
+	li x6, 0x6d11b01d
+	csrrw x4, 768, x6
+	li x6, 0x005a580a
+	bne x6, x4, csr_fail
+	li x6, 0xa5a5a5a5
+	csrrs x4, 768, x6
+	li x6, 0x0011b008
+	bne x6, x4, csr_fail
+	li x6, 0x5a5a5a5a
+	csrrs x4, 768, x6
+	li x6, 0x8035b1a8
+	bne x6, x4, csr_fail
+	li x6, 0x4eac03c8
+	csrrs x4, 768, x6
+	li x6, 0x807ff9aa
+	bne x6, x4, csr_fail
+	li x6, 0xa5a5a5a5
+	csrrc x4, 768, x6
+	li x6, 0x807ff9aa
+	bne x6, x4, csr_fail
+	li x6, 0x5a5a5a5a
+	csrrc x4, 768, x6
+	li x6, 0x005a580a
+	bne x6, x4, csr_fail
+	li x6, 0x05f68555
+	csrrc x4, 768, x6
+	li x6, 0x00000000
+	bne x6, x4, csr_fail
+	csrrwi x4, 768, 0b00101
+	li x6, 0x00000000
+	bne x6, x4, csr_fail
+	csrrwi x4, 768, 0b11010
+	li x6, 0x00000000
+	bne x6, x4, csr_fail
+	csrrwi x4, 768, 0b11010
+	li x6, 0x0000000a
+	bne x6, x4, csr_fail
+	csrrsi x4, 768, 0b00101
+	li x6, 0x0000000a
+	bne x6, x4, csr_fail
+	csrrsi x4, 768, 0b11010
+	li x6, 0x0000000a
+	bne x6, x4, csr_fail
+	csrrsi x4, 768, 0b11111
+	li x6, 0x0000000a
+	bne x6, x4, csr_fail
+	csrrci x4, 768, 0b00101
+	li x6, 0x0000000a
+	bne x6, x4, csr_fail
+	csrrci x4, 768, 0b11010
+	li x6, 0x0000000a
+	bne x6, x4, csr_fail
+	csrrci x4, 768, 0b11010
+	li x6, 0x00000000
+	bne x6, x4, csr_fail
+	csrr x4, 768
+	li x6, 0x00000000
+	bne x6, x4, csr_fail
+csr_pass:
+	li x1, 0
+	slli x1, x1, 1
+	addi x1, x1, 1
+	sw x1, tohost, t5
+	self_loop: j self_loop
+
+csr_fail:
+	li x1, 1
+	slli x1, x1, 1
+	addi x1, x1, 1
+	sw x1, tohost, t5
+	self_loop_2: j self_loop_2
+RVMODEL_DATA_BEGIN
+RVMODEL_DATA_END 
+
+

verif/tests/custom/CSR/csr_access_failing_tests/riscv_mvendorid_csr_test_0.S

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+// Copyright 2023 Thales
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+#include "model_test.h"
+.macro init
+.endm
+.section .text.init
+.globl _start
+.option norvc
+.org 0x00
+_start:
+	la x6, exception_handler  
+        csrw mtvec, x6  ## Load the address of the exception handler into MTVEC
+	csrw 0x341, x0
+    	csrw 0x342, x0
+
+
+	csrr x31, 3857
+	li x30, 0x00000602
+	# CSR_MVENDORID
+	li x12, 0xa5a5a5a5
+	csrrw x3, 3857, x12
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	li x12, 0x5a5a5a5a
+	csrrw x3, 3857, x12
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	li x12, 0x6165b321
+	csrrw x3, 3857, x12
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	li x12, 0xa5a5a5a5
+	csrrs x3, 3857, x12
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	li x12, 0x5a5a5a5a
+	csrrs x3, 3857, x12
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	li x12, 0x28b3f1dd
+	csrrs x3, 3857, x12
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	li x12, 0xa5a5a5a5
+	csrrc x3, 3857, x12
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	li x12, 0x5a5a5a5a
+	csrrc x3, 3857, x12
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	li x12, 0x12f4a94a
+	csrrc x3, 3857, x12
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	csrrwi x3, 3857, 0b00101
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	csrrwi x3, 3857, 0b11010
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	csrrwi x3, 3857, 0b00000
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	csrrsi x3, 3857, 0b00101
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	csrrsi x3, 3857, 0b11010
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	csrrsi x3, 3857, 0b11110
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	csrrci x3, 3857, 0b00101
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	csrrci x3, 3857, 0b11010
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	csrrci x3, 3857, 0b00110
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+	csrr x3, 3857
+	li x12, 0x00000602
+	bne x12, x3, csr_fail
+
+	j csr_pass
+
+exception_handler:
+csrr x30, 0x341	    ## Reading MEPC CSR which holds exception origin Address		
+csrr x31, 0x342     ## Reading MCAUSE CSR which holds the cause of exception
+addi x2, x2,2
+beq x31, x2, next   ## Checking is exception is expected exception or not
+j csr_fail
+
+next:
+addi x1, x1, 0
+bne x30, x1, next_iter  ## If MEPC has non-zero value then jump to next_iter
+j csr_fail
+
+next_iter:
+li x2, 0 		## Initilizing 0 in x2 register where MCAUSE value is previously stored
+addi x7, x30, 4
+jr x7			## Jump to MEPC + 4 Address location
+
+
+csr_pass:
+	li x1, 0
+	slli x1, x1, 1
+	addi x1, x1, 1
+	sw x1, tohost, t5
+	self_loop: j self_loop
+
+csr_fail:
+	li x1, 1
+	slli x1, x1, 1
+	addi x1, x1, 1
+	sw x1, tohost, t5
+	self_loop_2: j self_loop_2
+
+RVMODEL_DATA_BEGIN
+RVMODEL_DATA_END