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Move assertion statement outside of always_comb block #2552

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merged 3 commits into from
Oct 23, 2024
Merged

Move assertion statement outside of always_comb block #2552

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629328c
Move timing statement outside of `always_comb` block
ricted98 Oct 17, 2024
c8b68ad
Merge branch 'master' into rt/tag-cmp-assertion
JeanRochCoulon Oct 22, 2024
b922c73
Merge branch 'master' into rt/tag-cmp-assertion
JeanRochCoulon Oct 23, 2024
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3 changes: 2 additions & 1 deletion core/cache_subsystem/tag_cmp.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -81,9 +81,11 @@
if (req_i[i]) break;
end

end

`ifndef SYNTHESIS
`ifndef VERILATOR
// assert that cache only hits on one way

Check warning on line 88 in core/cache_subsystem/tag_cmp.sv

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[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
core/cache_subsystem/tag_cmp.sv:88:-    // assert that cache only hits on one way
core/cache_subsystem/tag_cmp.sv:89:-    // this only needs to be checked one cycle after all ways have been requested
core/cache_subsystem/tag_cmp.sv:90:-    onehot :
core/cache_subsystem/tag_cmp.sv:91:-    assert property (@(posedge clk_i) disable iff (!rst_ni) &req_i |=> $onehot0(hit_way_o))
core/cache_subsystem/tag_cmp.sv:92:-    else begin
core/cache_subsystem/tag_cmp.sv:93:-      $fatal(1, "Hit should be one-hot encoded");
core/cache_subsystem/tag_cmp.sv:94:-    end
core/cache_subsystem/tag_cmp.sv:88:+  // assert that cache only hits on one way
core/cache_subsystem/tag_cmp.sv:89:+  // this only needs to be checked one cycle after all ways have been requested
core/cache_subsystem/tag_cmp.sv:90:+  onehot :
core/cache_subsystem/tag_cmp.sv:91:+  assert property (@(posedge clk_i) disable iff (!rst_ni) &req_i |=> $onehot0(hit_way_o))
core/cache_subsystem/tag_cmp.sv:92:+  else begin
core/cache_subsystem/tag_cmp.sv:93:+    $fatal(1, "Hit should be one-hot encoded");
core/cache_subsystem/tag_cmp.sv:94:+  end
// this only needs to be checked one cycle after all ways have been requested
onehot :
assert property (@(posedge clk_i) disable iff (!rst_ni) &req_i |=> $onehot0(hit_way_o))
Expand All @@ -92,7 +94,6 @@
end
`endif
`endif
end

always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
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