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Remove dead and redundant code (#124)
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Signed-off-by: Szymon Bieganski <[email protected]>
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szbieg authored Jul 20, 2023
1 parent a0f5aaf commit 7836dae
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Showing 3 changed files with 1 addition and 5 deletions.
3 changes: 0 additions & 3 deletions rtl/cve2_controller.sv
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,6 @@ module cve2_controller #(
input logic [31:0] lsu_addr_last_i, // for mtval
input logic load_err_i,
input logic store_err_i,
output logic id_exception_o, // Instruction in ID taking an exception

// jump/branch signals
input logic branch_set_i, // branch set signal (branch definitely
Expand Down Expand Up @@ -215,8 +214,6 @@ module cve2_controller #(
// LSU exception requests
assign exc_req_lsu = store_err_i | load_err_i;

assign id_exception_o = exc_req_d;

// special requests: special instructions, pipeline flushes, exceptions...
// All terms in these expressions are qualified by instr_valid_i except exc_req_lsu which can come
// from the Writeback stage with no instr_valid_i from the ID stage
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2 changes: 1 addition & 1 deletion rtl/cve2_core.sv
Original file line number Diff line number Diff line change
Expand Up @@ -960,7 +960,7 @@ module cve2_core import cve2_pkg::*; #(
// Factor in exceptions taken in ID so RVFI tracking picks up flushed instructions that took
// a trap
assign rvfi_id_done = instr_id_done | (id_stage_i.controller_i.rvfi_flush_next &
id_stage_i.controller_i.id_exception_o);
id_stage_i.controller_i.exc_req_d);

// Without writeback stage first RVFI stage is output stage so simply valid the cycle after
// instruction leaves ID/EX (and so has retired)
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1 change: 0 additions & 1 deletion rtl/cve2_id_stage.sv
Original file line number Diff line number Diff line change
Expand Up @@ -494,7 +494,6 @@ module cve2_id_stage #(
.lsu_addr_last_i(lsu_addr_last_i),
.load_err_i (lsu_load_err_i),
.store_err_i (lsu_store_err_i),
.id_exception_o (),
// jump/branch control
.branch_set_i (branch_set),
.branch_not_set_i (branch_not_set),
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