move nmi to irq 32

[davideschiavone]

No description provided.

[christian-herber-nxp]

@szbieg: Davide would like to see SEC run on this, with the follwing contraints:

• nmi set to 0
• irq_fast[15] set to 0

[LeeHoff]

@davideschiavone will you also change cve2_top_tracing.sv to match cve2_top. We are using cve2_top_tracing in verification.

[szbieg]

Beside fixing the following external input signals:

• nmi set to 0
• irq_fast[15] set to 0
  equivalence is confirmed after fixing the internal write data bus to constant 32'b0:
• cs_registers_i.csr_wdata_int
• cve2_core_imp.cs_registers_i.csr_wdata_int

[davideschiavone]

Beside fixing the following external input signals:

• nmi set to 0
• irq_fast[15] set to 0
  equivalence is confirmed after fixing the internal write data bus to constant 32'b0:
• cs_registers_i.csr_wdata_int
• cve2_core_imp.cs_registers_i.csr_wdata_int

the NMI interrupt has been tested as well, when the core jumps to the NMI, it jumps to the ISR number 32, the mcause registers switches to 0x60 (MSB=1 interrupt, plus 32 in the bits 5:0) and the CSRR instruction on MCAUSE reports correctly 0x8000_0020`, i.e. interrupt 32.