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Feature/specification improvements #148

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merged 3 commits into from
Dec 21, 2023
Merged

Feature/specification improvements #148

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48d32b4
Fixed wrong OBI version referenced
christian-herber-nxp Sep 7, 2023
4eab586
Removing interrupt controller from coreplex components
christian-herber-nxp Sep 7, 2023
c63271c
Removing requirement to encode supervisor mode in AHB as supervisor m…
christian-herber-nxp Sep 7, 2023
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31 changes: 11 additions & 20 deletions doc/01_specification/index.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,8 @@ As displayed in the above figure, the IP comprises:

- The CV32E20 processor core with dual 32-bit Harvard memory interfaces

- Instruction fetch bus, data load/store bus
- Instruction fetch bus, data load/store bus. Protocol is protocol is
[OPENHW-OBI]_

- Support for both RV32I (32 x 32b GPRs) and RV32E (16 x 32b GPRs)

Expand All @@ -100,18 +101,11 @@ As displayed in the above figure, the IP comprises:

- Support for basic set of Configuration & Status Registers (CSRs)

- Dual 32-bit Harvard memory interfaces

- Supported core protocol is OBI_1_v1.2 (Open Bus Interface)
definition

At the coreplex design level, the following functions are added to the
processor core:

- Debug module including the :term:`DTM`

- Interrupt module

- System bus wrappers to convert from OBI [OPENHW-OBI]_ to the
:term:`AMBA`-:term:`AHB` (Advanced Microcontroller Bus Architecture, Advanced
High-performance Bus) protocol [AMBA-AHB]_
Expand Down Expand Up @@ -248,7 +242,7 @@ Operating modes (Privilege Levels)
| PVL-10 | CV32E20 shall support only little-endian memory |
| | organizations. |
+--------+--------------------------------------------------------------+
| PVL-20 | CV32E20 shall support **machine** and **unprivileged** |
| PVL-20 | CV32E20 shall support **machine** and **user** |
| | privilege modes. |
+--------+--------------------------------------------------------------+
| PVL-30 | CV32E20 shall export the CPU's operating mode as an address |
Expand Down Expand Up @@ -394,13 +388,13 @@ The implemented set of CSRs includes the following registers:
| | |
| | *0xb8c mpmcounter12h // HPM-20: upper word of mpmcounter12* |
| | |
| | 0xc00 cycle // unprivileged mode cycle, lower 32b |
| | 0xc00 cycle // user mode cycle, lower 32b |
| | |
| | 0xc02 instret // unprivileged mode instret, lower 32b |
| | 0xc02 instret // user mode instret, lower 32b |
| | |
| | 0xc80 cycleh // unprivileged mode cycle, upper 32b |
| | 0xc80 cycleh // user mode cycle, upper 32b |
| | |
| | 0xc82 instreth // unprivileged mode instret, upper 32b |
| | 0xc82 instreth // user mode instret, upper 32b |
| | |
| | 0xf11 mvendorid // machine vendor ID |
| | |
Expand Down Expand Up @@ -442,13 +436,13 @@ lower order 32-bit register.
| | |
| | 0xb82 minstreth // machine mode instret, upper 32 bits |
| | |
| | 0xc00 cycle // unprivileged mode cycle, lower 32b |
| | 0xc00 cycle // user mode cycle, lower 32b |
| | |
| | 0xc02 instret // unprivileged mode instret, lower 32b |
| | 0xc02 instret // user mode instret, lower 32b |
| | |
| | 0xc80 cycleh // unprivileged mode cycle, upper 32b |
| | 0xc80 cycleh // user mode cycle, upper 32b |
| | |
| | 0xc82 instreth // unprivileged mode instret, upper 32b |
| | 0xc82 instreth // user mode instret, upper 32b |
+--------+---------------------------------------------------------------+
| HPM-20 | CV32E20 should support 10 optional event counters |
| | (mhpmcounterX{h}) and their associated event selector |
Expand Down Expand Up @@ -667,9 +661,6 @@ CV32E20 coreplex memory bus
| | if E20 core mode = user, then {HNONSECURE, HPROT[1]} = |
| | 2'b10 |
| | |
| | if E20 core mode = supervisor, then {HNONSECURE, HPROT[1]} |
| | = 2'b11 |
| | |
| | if E20 core mode = machine, then {HNONSECURE, HPROT[1]} = |
| | 2'b01 |
+--------+-------------------------------------------------------------+
Expand Down
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