Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Update the interrupt vector table in the documentation #273

Open
wants to merge 5 commits into
base: main
Choose a base branch
from
Open

Update the interrupt vector table in the documentation #273

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
65d53a7
Add comment on cve2_controller about irq_fast
DanieleParravicini-Synthara Jun 10, 2024
e315edd
Update cve2 docs about boot_addr_i
DanieleParravicini-Synthara Jun 10, 2024
2a9f3c6
Add interrupt vector table description
DanieleParravicini-Synthara Jun 10, 2024
f40ce9c
Fixes Entry0 of interrupt vector table
DanieleParravicini-Synthara Jun 13, 2024
e022a30
Replace Ibex with CV32E20 in doc indices
DanieleParravicini-Synthara Jun 13, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 4 additions & 4 deletions doc/02_user/index.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
Ibex User Guide
===============
CV32E20 User Guide
==================

The Ibex User Guide provides all necessary information to use Ibex.
It is aimed at hardware developers integrating Ibex into a design, and software developers writing software running on Ibex.
The CV32E20 User Guide provides all necessary information to use CV32E20.
It is aimed at hardware developers integrating CV32E20 into a design, and software developers writing software running on CV32E20.

.. toctree::
:maxdepth: 1
Expand Down
2 changes: 1 addition & 1 deletion doc/02_user/integration.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -130,7 +130,7 @@ Interfaces
| | | | from :ref:`csr-mhartid` CSR |
+----------------------------+-------------------------+-----+----------------------------------------+
| ``boot_addr_i`` | 32 | in | First program counter after reset |
| | | | = ``boot_addr_i`` + 0x80, |
| | | | = ``boot_addr_i``, |
| | | | see :ref:`exceptions-interrupts` |
+----------------------------+-------------------------+-----+----------------------------------------+
| ``instr_*`` | Instruction fetch interface, see :ref:`instruction-fetch` |
Expand Down
130 changes: 113 additions & 17 deletions doc/03_reference/exception_interrupts.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,18 +3,18 @@
Exceptions and Interrupts
=========================

Ibex implements trap handling for interrupts and exceptions according to the RISC-V Privileged Specification, version 1.11.
Ibex implements trap handling for interrupts and exceptions according to the `RISC-V Privileged Specification, version 20211203 <https://drive.google.com/file/d/1EMip5dZlnypTk7pt4WWUKmtjUKTOkBqh/view>`_.

When entering an interrupt/exception handler, the core sets the ``mepc`` CSR to the current program counter and saves ``mstatus``.MIE to ``mstatus``.MPIE.
All exceptions cause the core to jump to the base address of the vector table in the ``mtvec`` CSR.
Interrupts are handled in vectored mode, i.e., the core jumps to the base address plus four times the interrupt ID.
Interrupts are handled in vectored mode, i.e., the core jumps to the base address plus the interrupt ID times 4.
Upon executing an MRET instruction, the core jumps to the program counter previously saved in the ``mepc`` CSR and restores ``mstatus``.MPIE to ``mstatus``.MIE.

The base address of the vector table is initialized to the boot address (must be aligned to 256 bytes, i.e., its least significant byte must be 0x00) when the core is booting.
The base address can be changed after bootup by writing to the ``mtvec`` CSR.
For more information, see the :ref:`cs-registers` documentation.

The core starts fetching at the address made by concatenating the most significant 3 bytes of the boot address and the reset value (0x80) as the least significant byte.
The core starts fetching at ``boot_addr_i``, see :ref:`core-integration` .
It is assumed that the boot address is supplied via a register to avoid long paths to the instruction fetch unit.

Privilege Modes
Expand All @@ -29,20 +29,21 @@ Interrupts

Ibex supports the following interrupts.

+-------------------------+-------+--------------------------------------------------+
| Interrupt Input Signal | ID | Description |
+=========================+=======+==================================================+
| ``irq_nm_i`` | 31 | Non-maskable interrupt (NMI) |
+-------------------------+-------+--------------------------------------------------+
| ``irq_fast_i[14:0]`` | 30:16 | 15 fast, local interrupts |
+-------------------------+-------+--------------------------------------------------+
| ``irq_external_i`` | 11 | Connected to platform-level interrupt controller |
+-------------------------+-------+--------------------------------------------------+
| ``irq_timer_i`` | 7 | Connected to timer module |
+-------------------------+-------+--------------------------------------------------+
| ``irq_software_i`` | 3 | Connected to memory-mapped (inter-processor) |
| | | interrupt register |
+-------------------------+-------+--------------------------------------------------+
+-------------------------+-------+------------------------------------------------------------+
| Interrupt Input Signal | ID | Description |
+=========================+=======+============================================================+
| ``irq_software_i`` | 3 | Connected to memory-mapped (inter-processor) |
| | | interrupt register (a.k.a. Machine software interrupt) |
+-------------------------+-------+------------------------------------------------------------+
| ``irq_timer_i`` | 7 | Connected to timer module (a.k.a. Machine timer interrupt) |
+-------------------------+-------+------------------------------------------------------------+
| ``irq_external_i`` | 11 | Connected to platform-level interrupt controller |
| | | (a.k.a. Machine external interrupt) |
+-------------------------+-------+------------------------------------------------------------+
| ``irq_fast_i[15:0]`` | 31:16 | 16 fast, local interrupts |
+-------------------------+-------+------------------------------------------------------------+
| ``irq_nm_i`` | 32 | Non-maskable interrupt (NMI) |
+-------------------------+-------+------------------------------------------------------------+

All interrupts except for the non-maskable interrupt (NMI) are controlled via the ``mstatus``, ``mie`` and ``mip`` CSRs.
After reset, all interrupts are disabled.
Expand Down Expand Up @@ -164,3 +165,98 @@ If a synchronous exception occurs whilst ``cpuctrl``.sync_exception_seen is set,

When a double fault is detected, the ``double_fault_seen_o`` output is asserted for one cycle and ``cpuctrl``.double_fault_seen is set.
Note that writing the ``cpuctrl``.double_fault_seen field has no effect on the ``double_fault_seen_o`` output.


Interrupt vector table
----------------------

The interrupt vector table is located at ``mtvec``, and each entry can contain the code for
the interrupt/exception handling.


When MODE=Direct, all traps into machine mode cause the pc to be set to the address in the BASE field.

When MODE=Vectored,

all synchronous exceptions into machine mode cause the pc to be set to the address in the BASE
field,

whereas interrupts cause the pc to be set to the address in the BASE field plus four times the
interrupt cause number.


From `RISC-V Privileged Specification, version 20211203, page 30 <https://drive.google.com/file/d/1EMip5dZlnypTk7pt4WWUKmtjUKTOkBqh/view>`_.

The following table indicates the offset of the entry and
its description.

+-------------------------+------------------------------------------------------------+
| offset in bytes | Description |
+=========================+============================================================+
| 0x00 | Exception |
+-------------------------+------------------------------------------------------------+
| 0x04 | reserved |
+-------------------------+------------------------------------------------------------+
| 0x08 | reserved |
+-------------------------+------------------------------------------------------------+
| 0x0c | Machine software interrupt |
+-------------------------+------------------------------------------------------------+
| 0x10 | reserved |
+-------------------------+------------------------------------------------------------+
| 0x14 | reserved |
+-------------------------+------------------------------------------------------------+
| 0x18 | reserved |
+-------------------------+------------------------------------------------------------+
| 0x1c | Machine timer interrupt |
+-------------------------+------------------------------------------------------------+
| 0x20 | reserved |
+-------------------------+------------------------------------------------------------+
| 0x24 | reserved |
+-------------------------+------------------------------------------------------------+
| 0x28 | reserved |
+-------------------------+------------------------------------------------------------+
| 0x2c | Machine external interrupt |
+-------------------------+------------------------------------------------------------+
| 0x30 | reserved |
+-------------------------+------------------------------------------------------------+
| 0x34 | reserved |
+-------------------------+------------------------------------------------------------+
| 0x38 | reserved |
+-------------------------+------------------------------------------------------------+
| 0x3c | reserved |
+-------------------------+------------------------------------------------------------+
| 0x40 | irq_fast_i[0] |
+-------------------------+------------------------------------------------------------+
| 0x44 | irq_fast_i[1] |
+-------------------------+------------------------------------------------------------+
| 0x48 | irq_fast_i[2] |
+-------------------------+------------------------------------------------------------+
| 0x4c | irq_fast_i[3] |
+-------------------------+------------------------------------------------------------+
| 0x50 | irq_fast_i[4] |
+-------------------------+------------------------------------------------------------+
| 0x54 | irq_fast_i[5] |
+-------------------------+------------------------------------------------------------+
| 0x58 | irq_fast_i[6] |
+-------------------------+------------------------------------------------------------+
| 0x5c | irq_fast_i[7] |
+-------------------------+------------------------------------------------------------+
| 0x60 | irq_fast_i[8] |
+-------------------------+------------------------------------------------------------+
| 0x64 | irq_fast_i[9] |
+-------------------------+------------------------------------------------------------+
| 0x68 | irq_fast_i[10] |
+-------------------------+------------------------------------------------------------+
| 0x6c | irq_fast_i[11] |
+-------------------------+------------------------------------------------------------+
| 0x70 | irq_fast_i[12] |
+-------------------------+------------------------------------------------------------+
| 0x74 | irq_fast_i[13] |
+-------------------------+------------------------------------------------------------+
| 0x78 | irq_fast_i[14] |
+-------------------------+------------------------------------------------------------+
| 0x7c | irq_fast_i[15] |
+-------------------------+------------------------------------------------------------+
| 0x80 | irq_nm_i |
+-------------------------+------------------------------------------------------------+

8 changes: 4 additions & 4 deletions doc/03_reference/index.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
Ibex Reference Guide
====================
CV32E20 Reference Guide
=======================

The Ibex Reference Guide provides background information.
It describes the design in detail, discusses the verification approach and the resulting testbench structures, and generally helps to understand Ibex in depth.
The CV32E20 Reference Guide provides background information.
It describes the design in detail, discusses the verification approach and the resulting testbench structures, and generally helps to understand CV32E20 in depth.

.. toctree::
:maxdepth: 2
Expand Down
3 changes: 2 additions & 1 deletion rtl/cve2_controller.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -499,9 +499,10 @@ module cve2_controller #(
exc_cause_o = EXC_CAUSE_IRQ_NM;
nmi_mode_d = 1'b1; // enter NMI mode
end else if (irqs_i.irq_fast != 16'b0) begin
// if any of the irq_fast is one
// generate exception cause ID from fast interrupt ID:
// - first bit distinguishes interrupts from exceptions,
// - third bit adds 16 to fast interrupt ID so that the interrup 0 becomes 16 and the interrupt 15 becomes 31 (hence 5bits)
// - third bit adds 16 to fast interrupt ID so that the interrupt 0 becomes 16 and the interrupt 15 becomes 31 (hence 5bits)
// - second bit is always 0 as the FAST interrupts are represented in the first 5bits, the 6th is always 0 cause is used by the NMI (in that case is 1 as represented by the number 32)
// for example EXC_CAUSE_IRQ_FAST_0 = {1'b1, 6'd16}
exc_cause_o = exc_cause_e'({3'b101, mfip_id});
Expand Down
Loading