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Re-implemented external reg-enable.
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Maurus Item committed Jul 10, 2024
1 parent 2877f21 commit f5e0339
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Showing 7 changed files with 65 additions and 24 deletions.
4 changes: 3 additions & 1 deletion src/fpnew_aux.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,8 @@ module fpnew_aux #(
output logic [NumPipeRegs-1:0] reg_enable_o,
output logic [NumPipeRegs-1:0] vector_reg_enable_o,
output logic [NumLanes-1:0][NumPipeRegs-1:0] lane_reg_enable_o,
// External register enable override
input logic [NumPipeRegs-1:0] reg_ena_i,
// Indication of valid data in flight
output logic busy_o
);
Expand Down Expand Up @@ -89,7 +91,7 @@ module fpnew_aux #(
`FFLARNC(valid[i+1], valid[i], ready[i], flush_i, 1'b0, clk_i, rst_ni)

// Enable register if pipleine ready and a valid data item is present
assign reg_ena = ready[i] & valid[i];
assign reg_ena = (ready[i] & valid[i]) | reg_ena_i[i];

// Drive external registers with reg enable
assign reg_enable_o[i] = reg_ena;
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39 changes: 32 additions & 7 deletions src/fpnew_aux_fsm.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -52,8 +52,12 @@ module fpnew_aux_fsm #(
// Signals for the Lane FSMs
// Signal to start the FSM, will be asserted for one cycle
output logic [NumLanes-1:0] lane_fsm_start_o,
// Signal to abort the current operation for the FSMs, will be asserted for one cycle
output logic [NumLanes-1:0] lane_fsm_kill_o,
// Signal that the FSM finished it's operation, should be asserted continuously
input logic [NumLanes-1:0] lane_fsm_ready_i,
// External register enable override
input logic [NumPipeRegs-1:0] reg_ena_i,
// Indication of valid data in flight
output logic busy_o
);
Expand Down Expand Up @@ -110,7 +114,7 @@ module fpnew_aux_fsm #(
`FFLARNC(in_valid[i+1], in_valid[i], in_ready[i], flush_i, 1'b0, clk_i, rst_ni)

// Enable register if pipleine ready and a valid data item is present
assign reg_ena = in_ready[i] & in_valid[i];
assign reg_ena = (in_ready[i] & in_valid[i]) | reg_ena_i[i];

// Drive external registers with reg enable
assign reg_enable_o[i] = reg_ena;
Expand Down Expand Up @@ -220,19 +224,40 @@ module fpnew_aux_fsm #(

`FF(state_q, state_d, IDLE);

// Mini FSM for external reg enable. If external reg enable is set:
// 1. Kill any ongoing operations
// 2. On the next cycle start new operations
logic ext_fsm_start_d, ext_fsm_start_q;

if (NUM_INP_REGS > 0) begin
assign ext_fsm_start_d = reg_ena_i[NUM_INP_REGS - 1];
end else begin
assign ext_fsm_start_d = 1'b0;
end

`FF(ext_fsm_start_q, ext_fsm_start_d, 1'b0);

// Kill Lanes where a new input is given
for (genvar l = 0; l < NumLanes; l++) begin
assign lane_fsm_kill_o[l] = ext_fsm_start_d && in_lane_active[NUM_INP_REGS][l];
end

// Start Lanes when FSM starts and lane is active
for (genvar l = 0; l < NumLanes; l++) begin
assign lane_fsm_start_o[l] = fsm_start && in_lane_active[NUM_INP_REGS][l];
assign lane_fsm_start_o[l] = (fsm_start || ext_fsm_start_q) && in_lane_active[NUM_INP_REGS][l];
end

// ----------------
// Data Holding FFs
// ----------------

`FFL( held_tag, in_tag[NUM_INP_REGS], fsm_start, TagType'('0));
`FFL( held_aux, in_aux[NUM_INP_REGS], fsm_start, AuxType'('0));
`FFL( held_is_vector, in_is_vector[NUM_INP_REGS], fsm_start, '0);
`FFL(held_lane_active, in_lane_active[NUM_INP_REGS], fsm_start, '0);
logic hold_reg_enable;
assign hold_reg_enable = fsm_start || ext_fsm_start_d;

`FFL( held_tag, in_tag[NUM_INP_REGS], hold_reg_enable, TagType'('0));
`FFL( held_aux, in_aux[NUM_INP_REGS], hold_reg_enable, AuxType'('0));
`FFL( held_is_vector, in_is_vector[NUM_INP_REGS], hold_reg_enable, '0);
`FFL(held_lane_active, in_lane_active[NUM_INP_REGS], hold_reg_enable, '0);

// ---------------
// Output pipeline
Expand Down Expand Up @@ -272,7 +297,7 @@ module fpnew_aux_fsm #(
`FFLARNC(out_valid[i+1], out_valid[i], out_ready[i], flush_i, 1'b0, clk_i, rst_ni)

// Enable register if pipleine ready and a valid data item is present
assign reg_ena = out_ready[i] & out_valid[i];
assign reg_ena = (out_ready[i] & out_valid[i]) | reg_ena_i[NUM_INP_REGS + i];;

// Drive external registers with reg enable
assign reg_enable_o[NUM_INP_REGS + i] = reg_ena;
Expand Down
29 changes: 15 additions & 14 deletions src/fpnew_divsqrt_multi.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,7 @@ module fpnew_divsqrt_multi #(
input logic flush_i,
input logic[NumPipeRegs-1:0] reg_enable_i,
input logic fsm_start_i,
input logic fsm_kill_i,
output logic fsm_ready_o
);

Expand Down Expand Up @@ -142,20 +143,20 @@ module fpnew_divsqrt_multi #(
fpnew_pkg::status_t unit_status;

div_sqrt_top_mvp i_divsqrt_lei (
.Clk_CI ( clk_i ),
.Rst_RBI ( rst_ni ),
.Div_start_SI ( div_valid ),
.Sqrt_start_SI ( sqrt_valid ),
.Operand_a_DI ( divsqrt_operands[0] ),
.Operand_b_DI ( divsqrt_operands[1] ),
.RM_SI ( rnd_mode_q ),
.Precision_ctl_SI ( '0 ),
.Format_sel_SI ( divsqrt_fmt ),
.Kill_SI ( flush_i ),
.Result_DO ( raw_unit_result ),
.Fflags_SO ( unit_status ),
.Ready_SO ( fsm_ready_o ),
.Done_SO ( unit_done )
.Clk_CI ( clk_i ),
.Rst_RBI ( rst_ni ),
.Div_start_SI ( div_valid ),
.Sqrt_start_SI ( sqrt_valid ),
.Operand_a_DI ( divsqrt_operands[0] ),
.Operand_b_DI ( divsqrt_operands[1] ),
.RM_SI ( rnd_mode_q ),
.Precision_ctl_SI ( '0 ),
.Format_sel_SI ( divsqrt_fmt ),
.Kill_SI ( flush_i | fsm_kill_i ),
.Result_DO ( raw_unit_result ),
.Fflags_SO ( unit_status ),
.Ready_SO ( fsm_ready_o ),
.Done_SO ( unit_done )
);

// Adjust result width and fix FP8
Expand Down
3 changes: 2 additions & 1 deletion src/fpnew_divsqrt_th_64_multi.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,7 @@ module fpnew_divsqrt_th_64_multi #(
input logic flush_i,
input logic[NumPipeRegs-1:0] reg_enable_i,
input logic fsm_start_i,
input logic fsm_kill_i,
output logic fsm_ready_o
);

Expand Down Expand Up @@ -258,7 +259,7 @@ module fpnew_divsqrt_th_64_multi #(
.idu_vfpu_rf_pipex_func ( {3'b0, divsqrt_fmt_q, 11'b0 ,sqrt_op, div_op} ), // Defines format (bits 16,15) and operation (bits 1,0)
.idu_vfpu_rf_pipex_gateclk_sel ( func_sel ), // 2. Select func
.pad_yy_icg_scan_en ( 1'b0 ), // SE signal for the redundant clock gating module
.rtu_yy_xx_flush ( flush_i ), // Flush
.rtu_yy_xx_flush ( flush_i | fsm_kill_i ), // Flush
.vfpu_yy_xx_dqnan ( 1'b0 ), // Disable qNaN, set to 1 if sNaN is used
.vfpu_yy_xx_rm ( rm_q ), // Round mode. redundant if imm0 set to the same
.pipex_dp_vfdsu_ereg ( ), // Don't care, used by C910
Expand Down
2 changes: 2 additions & 0 deletions src/fpnew_opgroup_block.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -132,6 +132,7 @@ module fpnew_opgroup_block #(
.tag_o ( fmt_outputs[fmt].tag ),
.out_valid_o ( fmt_out_valid[fmt] ),
.out_ready_i ( fmt_out_ready[fmt] ),
.reg_ena_i ( '0 ),
.busy_o ( fmt_busy[fmt] )
);
// If the format wants to use merged ops, tie off the dangling ones not used here
Expand Down Expand Up @@ -207,6 +208,7 @@ module fpnew_opgroup_block #(
.tag_o ( fmt_outputs[FMT].tag ),
.out_valid_o ( fmt_out_valid[FMT] ),
.out_ready_i ( fmt_out_ready[FMT] ),
.reg_ena_i ( '0 ),
.busy_o ( fmt_busy[FMT] )
);

Expand Down
3 changes: 3 additions & 0 deletions src/fpnew_opgroup_fmt_slice.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,8 @@ module fpnew_opgroup_fmt_slice #(
// Output handshake
output logic out_valid_o,
input logic out_ready_i,
// External register enable override
input logic [NumPipeRegs-1:0] reg_ena_i,
// Indication of valid data in flight
output logic busy_o
);
Expand Down Expand Up @@ -104,6 +106,7 @@ module fpnew_opgroup_fmt_slice #(
.lane_active_o ( out_lane_active ),
.out_valid_o,
.out_ready_i,
.reg_ena_i,
.busy_o,
.reg_enable_o ( /* Unused */ ),
.vector_reg_enable_o ( /* Unused */ ),
Expand Down
9 changes: 8 additions & 1 deletion src/fpnew_opgroup_multifmt_slice.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,8 @@ module fpnew_opgroup_multifmt_slice #(
// Output handshake
output logic out_valid_o,
input logic out_ready_i,
// External register enable override
input logic [NumPipeRegs-1:0] reg_ena_i,
// Indication of valid data in flight
output logic busy_o
);
Expand Down Expand Up @@ -152,7 +154,7 @@ FP8. Please use the PULP DivSqrt unit when in need of div/sqrt operations on FP8
// Signals to transmit reg enable to other modules
logic [NumPipeRegs-1:0] vector_reg_enable;

logic [NUM_LANES-1:0] in_lane_active, out_lane_active, lane_fsm_ready, lane_fsm_start;
logic [NUM_LANES-1:0] in_lane_active, out_lane_active, lane_fsm_ready, lane_fsm_start, lane_fsm_kill;
logic [NUM_LANES-1:0][NumPipeRegs-1:0] lane_reg_enabe;

if (OpGroup == fpnew_pkg::DIVSQRT) begin: gen_fsm_aux
Expand All @@ -178,11 +180,13 @@ FP8. Please use the PULP DivSqrt unit when in need of div/sqrt operations on FP8
.lane_active_o ( out_lane_active ),
.out_valid_o,
.out_ready_i,
.reg_ena_i,
.busy_o,
.reg_enable_o ( /* Unused */ ),
.vector_reg_enable_o ( vector_reg_enable ),
.lane_reg_enable_o ( lane_reg_enabe ),
.lane_fsm_start_o ( lane_fsm_start ),
.lane_fsm_kill_o ( lane_fsm_kill ),
.lane_fsm_ready_i ( lane_fsm_ready )
);
end else begin: gen_direct_aux
Expand All @@ -207,6 +211,7 @@ FP8. Please use the PULP DivSqrt unit when in need of div/sqrt operations on FP8
.lane_active_o ( out_lane_active ),
.out_valid_o,
.out_ready_i,
.reg_ena_i,
.busy_o,
.reg_enable_o ( /* Unused */ ),
.vector_reg_enable_o ( vector_reg_enable ),
Expand Down Expand Up @@ -354,6 +359,7 @@ FP8. Please use the PULP DivSqrt unit when in need of div/sqrt operations on FP8
.mask_o ( lane_masks[lane] ),
.reg_enable_i ( lane_reg_enabe[lane] ),
.fsm_start_i ( lane_fsm_start[lane] ),
.fsm_kill_i ( lane_fsm_kill[lane] ),
.fsm_ready_o ( lane_fsm_ready[lane] )
);
end else begin : gen_pulp_divsqrt
Expand All @@ -377,6 +383,7 @@ FP8. Please use the PULP DivSqrt unit when in need of div/sqrt operations on FP8
.mask_o ( lane_masks[lane] ),
.reg_enable_i ( lane_reg_enabe[lane] ),
.fsm_start_i ( lane_fsm_start[lane] ),
.fsm_kill_i ( lane_fsm_kill[lane] ),
.fsm_ready_o ( lane_fsm_ready[lane] )
);
end
Expand Down

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