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@alainmarcel SureLog - UHDM

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    12 repositories

    • Surelog

      Public
      SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
      C++
      •
      Apache License 2.0
      •69•25•0•0•Updated Oct 7, 2024Oct 7, 2024

    • UHDM

      Public
      Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
      C++
      •
      Apache License 2.0
      •40•15•0•0•Updated Oct 7, 2024Oct 7, 2024

    • yosys-uhdm-plugin-integration

      Public
      Python
      •
      Apache License 2.0
      •21•2•0•0•Updated Sep 1, 2023Sep 1, 2023

    • sv-tests

      Public
      Test suite designed to check compliance with the SystemVerilog standard.
      SystemVerilog
      •
      ISC License
      •75•0•0•0•Updated Jul 30, 2023Jul 30, 2023

    • antlr4

      Public
      ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.
      Java
      •
      Other
      •3.3k•0•0•0•Updated Apr 13, 2022Apr 13, 2022

    • simview

      Public
      C++
      •
      MIT License
      •6•0•0•0•Updated Jan 23, 2022Jan 23, 2022

    • UHDM-integration-tests

      Public
      C++
      •
      Apache License 2.0
      •8•0•0•0•Updated Jun 22, 2021Jun 22, 2021

    • EasyCLA-code_only

      Public
      34•0•0•0•Updated Jun 10, 2021Jun 10, 2021

    • tsc

      Public
      CHIPS Alliance Technical Steering Committee
      Apache License 2.0
      •22•0•0•0•Updated May 25, 2021May 25, 2021

    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      •
      ISC License
      •891•0•0•0•Updated Nov 14, 2020Nov 14, 2020

    • Help_Wanted

      Public
      Ideas that need engineering-power from the community for UHDM/Surelog/Related topics
      MIT License
      •0•2•4•0•Updated Oct 14, 2020Oct 14, 2020

    • verilator

      Public
      C++
      •
      GNU Lesser General Public License v3.0
      •5•0•0•0•Updated Feb 13, 2020Feb 13, 2020