long_run.json

{
    "BENCHMARKS": {
        "LU8PEEng": {
            "design":"RTL_Benchmark/Verilog/VTR_design/LU8PEEng/rtl/config.tcl",
           "CLOCK_DATA": {
                "Clock1": "clk"
            }
        },
        "CH_DFSIN": {
            "design":"RTL_Benchmark/Verilog/ql_design/CH_DFSIN/rtl/config.tcl",
           "CLOCK_DATA": {
                "Clock1": "clk"
            }
        },
        "LU32PEEng": {
            "design":"RTL_Benchmark/Verilog/ql_design/LU32PEEng/rtl/config.tcl",
           "CLOCK_DATA": {
                "Clock1": "i_clk"
            }
        },
        "mcml": {
            "design":"RTL_Benchmark/Verilog/ql_design/mcml/rtl/config.tcl",
           "CLOCK_DATA": {
                "Clock1": "clk"
            }
        },
        "sctag": {
            "design":"RTL_Benchmark/Verilog/ql_design/sctag/rtl/config.tcl",
           "CLOCK_DATA": {
                "Clock1": "cmp_gclk"
            }
        },
        "smithwaterman": {
            "design":"RTL_Benchmark/Verilog/ql_design/smithwaterman/rtl/config.tcl",
           "CLOCK_DATA": {
                "Clock1": "ap_clk"
            }
        },
        "stereovision2": {
            "design":"RTL_Benchmark/Verilog/ql_design/stereovision2/wrapper_rtl/config.tcl",
           "CLOCK_DATA": {
                "Clock1": "tm3_clk_v0"
            }
        },
        "syn2": {
            "design":"RTL_Benchmark/Verilog/ql_design/syn2/rtl/config.tcl",
           "CLOCK_DATA": {
                "Clock1": "clock"
            }
        }
    }
}