GitHub - os-fpga/RTL_Benchmark: This repository contains the benchmarks.

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This repository contains the benchmarks.

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Name		Name	Last commit message	Last commit date
Latest commit History 564 Commits
.github		.github
SVerilog		SVerilog
VHDL		VHDL
Verilog		Verilog
other		other
LICENSE		LICENSE
large_design.json		large_design.json
long_run.json		long_run.json
macro_benchmarks.json		macro_benchmarks.json
meso_benchmarks.json		meso_benchmarks.json
micro-benchmarks.json		micro-benchmarks.json
path_list.txt		path_list.txt
plain_luts.json		plain_luts.json
replace.py		replace.py
scalable.json		scalable.json
unsynthesizable_yosys.json		unsynthesizable_yosys.json

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Copyright (c) 2022-2024 Rapid Silicon Inc.

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it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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