Rapid Silicon Raptor Design Suite
Raptor is a classic RTL (User design + IPs) 2 Bitstream FPGA compiler. It can be ran in batch mode or GUI mode with complete Tcl scripting capability.
Please refer User Guide
Please refer BUILD.md.
Please see INSTALL.md.
raptor --help
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
=-= Rapid Silicon Raptor Design Suite Help =-=
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
Command-line Options:
--help : Help
--version : Tool version
--batch : Tcl only, no GUI
--script <script>: Execute a Tcl script
--project <project file>: Open a project
--mute : Mutes stdout in batch mode
Tcl commands (Available in GUI or Batch console or Batch script):
---------------
--- General ---
---------------
help : Help
---------------
--- Project ---
---------------
create_design <name> ?clean? ?-type <project type>? : Creates a design with <name> name
<project type> : rtl (Default), gate-level
clean : If project folder already exists, remove recursively folder content
open_project <file> : Opens a project
run_project <file> : Opens and immediately runs the project
target_device <name> : Targets a device with <name>
device_file <file> : Set file <file> with supported devices which replaces default file (device.xml)
add_design_file <file list> ?type? ?-work <libName>? ?-L <libName>?
<type> : -VHDL_1987, -VHDL_1993, -VHDL_2000, -VHDL_2008, -VHDL_2019, -V_1995, -V_2001, -SV_2005, -SV_2009, -SV_2012, -SV_2017, default auto-detect
-work <libName> : Compiles the compilation unit into library <libName>, default is "work"
-L <libName> : Import the library <libName> needed to compile the compilation unit, default is "work"
set_top_module <top> ?-work <libName>? : Sets the top-level design module/entity for synthesis
add_include_path <paths> : Specify paths for Verilog includes (Not applicable to VHDL)
add_library_path <paths> : Specify paths for libraries (Not applicable to VHDL)
add_library_ext <ext> : Spcify library extensions (Not applicable to VHDL)
set_macro <name>=<value> : As in -D<macro>=<value>
read_netlist <file> : Read a netlist (.blif/.eblif) instead of an RTL design (Skip Synthesis)
add_constraint_file <file> : Sets constraints file (SDC) filename and location
add_simulation_file <file list> ?type? ?-work <libName>? ?-L <libName>?
<type> : -VHDL_1987, -VHDL_1993, -VHDL_2000, -VHDL_2008, -VHDL_2019, -V_1995, -V_2001, -SV_2005, -SV_2009, -SV_2012, -SV_2017, -C, -CPP
-work <libName> : Compiles the compilation unit into library <libName>, default is "work"
-L <libName> : Import the library <libName> needed to compile the compilation unit, default is "work"
set_top_testbench <module> : Sets the top-level testbench module/entity for simulation
clear_simulation_files : Remove all simulation files
script_path : Returns the path of the Tcl script passed with --script
max_threads <-1/[2:64]> : Maximum number of threads to be used (-1 is for automatic selection)
--------------------
--- Design query ---
--------------------
all_inputs : Return all input ports for the current design.
all_outputs : Return all output ports for the current design.
get_ports <pattern> : Return all ports for the current design that match a specified pattern. If pattern is empty, get_ports returns empty string.
<pattern> : Examples of supported patterns: {*}, {cl*}, {d[0]}, {clock}, {clock1 clock2}
-------------------
--- Constraints ---
-------------------
keep <signal list> OR all_signals : Keeps the list of signals or all signals through Synthesis unchanged (unoptimized in certain cases)
message_severity <message_id> <ERROR/WARNING/INFO/IGNORE> : Upgrade/downgrade message severity
----------
--- IP ---
----------
add_litex_ip_catalog <directory> : Browses directory for LiteX IP generators, adds the IP(s) to the IP Catalog
ip_catalog ?<ip_name>? : Lists all available IPs, and their parameters if <ip_name> is given
configure_ip <IP_NAME> -mod_name <name> -out_file <filename> -version <ver_name> -P<param>="<value>"...
: Configures an IP <IP_NAME> and generates the corresponding file with module name
ipgenerate ?clean? : Generates all IP instances set by ip_configure
clean : Deletes files generated from this task
simulate_ip <module name> : Simulate IP with module name <module name>
------------------
--- Simulation ---
------------------
simulation_options <simulator> <phase> ?<level>? <options> : Sets the simulator specific options for the specified phase
<phase> : compilation, elaboration, simulation, extra_options
simulate <level> ?<simulator>? ?<waveform_file>?: Simulates the design and testbench
<level> : rtl, gate, pnr, timed_pnr. rtl: RTL simulation, gate: post-synthesis simulation, pnr: post-pnr simulation, timed_pnr: post-pnr timing-annotated simulation
<simulator> : verilator, ghdl, icarus
wave_* : All wave commands will launch a GTKWave process if one hasn't been launched already. Subsequent commands will be sent to the launched process.
wave_cmd ... : Sends given tcl commands to GTKWave process. See GTKWave docs for gtkwave:: commands.
wave_open <filename> : Load given file in current GTKWave process.
wave_refresh : Reloads the current active wave file
wave_show <signal> : Add the given signal to the GTKWave window and highlight it.
wave_time <time> : Set the primary marker to <time>. Time units can be specified, without a space. Ex: wave_time 100ps.
setup_lec_sim ?<clock_period>? ?<iteration_level>?: Generates a "RTL vs gate-level" and "RTL vs post-pnr" automatic testbench (Invoke after Synthesis)
<clock_period>: Clock period in ns
<iteration_level>: Simulation clock cycles, level 0 - 100, level 1 - 1000, level 2 - 2000
-----------------
--- Synthesis ---
-----------------
synth_options <option list>:
-effort <level> : Optimization effort level (high, medium, low)
high : Most compute, generally impacting runtime (default)
medium : Balanced compute
low : least compute, least runtime
-fsm_encoding <encoding> : FSM encoding (binary, onehot)
binary : Compact encoding - using minimum of registers to cover the N states
onehot : One hot encoding - using N registers for N states (default)
-carry <mode> : Carry logic inference mode (all, auto, none)
all : Infer as much as possible
auto : Infer carries based on internal heuristics (default)
none : Do not infer carries
-clke_strategy <strategy>: Clock enable extraction strategy for FFs (early, late)
early : Perform early extraction (default)
late : Perform late extraction
-fast : Perform the fastest synthesis. QoR can be impacted.
-no_flatten : Do not flatten design.
-no_simplify : Do not run special simplification algorithms in synthesis.
-no_tribuf : Do not preserve I/O tristate buffers
-no_adder : Do not infer adders
-inferred_io : Automatic I/O inference (Default false for eFPGA)
-no_inferred_io : No automatic I/O inference (Default true for FPGA)
set_limits <type> <int> : Sets a user limit on object of type (dsp, bram), specify 0 to disable block inferrence
dsp : Maximum number of usable DSPs
bram : Maximum number of usable BRAMs
analyze ?clean? : Analyzes the RTL design, generates top-level, pin and hierarchy information
clean : Deletes files generated from this task
synthesize <optimization> ?clean? : RTL Synthesis, optional opt. (area, delay, mixed)
<optimization> : area, delay, mixed
area : Optimize for reduce resource area
delay : Optimize for performance
mixed : Optimize for area and performance (default)
clean : Deletes files generated from this task
---------------
--- Packing ---
---------------
pnr_netlist_lang <format> : Chooses post-synthesis netlist format, (blif, eblif, edif, verilog, vhdl)
packing_options <option list>: Packing options
-clb_packing <directive> : Performance optimization flags (auto, dense, timing_driven)
auto : CLB packing automatically determined (default)
dense : Pack logic more densely into CLBs resulting in fewer utilized CLBs however may negatively impact timing
timing_driven : Pack logic to optimize timing
packing ?clean? : Packing
clean : Deletes files generated from this task
-------------
--- Place ---
-------------
pin_loc_assign_method <method>: Algortihm for automatic pin assignment (in_define_order, random, pin_constraint_disabled)
in_define_order : Port order pin assignment (default)
random : Random pin assignment
pin_constraint_disabled: No automatic pin assignment
place ?clean? : Placer
clean : Deletes files generated from this task
pnr_options <option list> : PnR Options
-------------
--- Route ---
-------------
route ?clean? : Router
clean : Deletes files generated from this task
------------------------------
--- Static Timing Analysis ---
------------------------------
sta ?clean? ?opensta? : Statistical Timing Analysis
clean : Deletes files generated from this task
opensta : Use OpenSTA tool for timing analysis
------------------------------
--- Power Analysis -----------
------------------------------
power ?clean? : Statistical Power Analysis
clean : Deletes files generated from this task
-----------------
--- Bitstream ---
-----------------
bitstream ?clean? : Bitstream generation
clean : Deletes files generated from this task
---------------------------------
--- Implementation Strategy ---
---------------------------------
timing_flow <"default" | "analytic"> : Timing driven compilation flow. This proc performs a series of steps in the design flow to achieve timing-driven placement and routing.
"analytic" : Use timing-driven analytic placement as initial placement. The result is then passed through the simulated annealing (SA) placer.
"default" : Uses VPR's default initial placer (default)
routability_flow <number_of_molecules_in_partition "200"> <congestion "medium | high"> <vpr_constraints_file ""> : Routability driven compilation flow. This proc accepts three optional arguments:
- number_of_molecules_in_partition: Average number of molecules in each cluster (default is 200).
- congestion: medium, high
- initial VPR placement constraints file
congestion_flow <congestion_type> : Congestion driven compilation flow
"uniform" : For uniformely congested high utilization designs
"hotspot" : For hotspots of congestion in moderately utilized designs
------------------
--- Programmer ---
------------------
programmer <command> : A programmer tool allows you to program and configure FPGA devices via JTAG
command : fpga_config, flash, fpga_status, list_device, list_cable, otp
fpga_config -c <cable name/index> ?-d <device_index>? <bitstream_file> : Program the FPGA device via JTAG
-c <cable_name/index> : Specify the cable name or index
-d <device_index> : Specify the device index
<bitstream_file> : Bitstream file to program
flash -c <cable name/index> ?-d <device_index>? ?-o <operations>? <bitstream_file> : Program the Flash via JTAG
-c <cable_name/index> : Specify the cable name or index
-d <device_index> : Specify the device index
-o <operations> : Specify the operations to perform on the flash (Valid operations: program)
<bitstream_file> : Bitstream file to program
fpga_status -c <cable name/index> -d <device_index> ?-v? : Query FPGA Configuration Done and Configuration IsError status for a specified device
-c <cable_name/index> : Specify the cable name or index
-d <device_index> : Specify the device index
-v : Verbose mode. Display additional information of fpga_status output
list_device ?-c <cable name/index>? ?-v?: List all available devices or specified cable devices
-c <cable_name/index> : Specify the cable name or index
-v : Verbose mode. Display additional information of list_device output
list_cable ?-v? : List all connected USB programmer cables
-v : Verbose mode. Display additional information of list_cable output
otp -c <cable name/index> -d <device_index> ?-y? <bitstream_file> : Program the device OTP via JTAG. WARNING: OTP programming is not reversible once programmed successfully.
-c <cable_name/index> : Specify the cable name or index
-d <device_index> : Specify the device index
-y : Indicate the consesus of the user to proceed with OTP programming.
<bitstream_file> : Bitstream file to program
---------------------
--- OCLA Debugger ---
---------------------
debugger <command>
list_cable ?-v? : To display all the connected/detected cables.
-v : Display additional information of list_cable output
list_device ?-v? : To display list of connected devices to each connected/detected cable.
-v : Display additional information of list_device output
info ?-b <cable name/index>? ?-d <device index>? : Command to display all probe information in the user design parsed from the .bitasm file. And the current OCLA global and trigger configuration.
-b <cable name/index> : Cable name or index
-d <device index> : Device index
load -f <filepath> : Start a debugging session with user design specified in a .bitasm file.
-f : Specify user design .bitasm file to start debugging
unload : Stop the debugging session and clear the loaded OCLA information.
config -n <clock domain id> ?-m <trigger mode>? ?-s <sample size>? ?-t <boolean condition>? ?-b <cable name/index>? ?-d <device index>? : To configure the global operation modes of a clock domain.
-n <clock domain id> : Clock domain ID
-m <trigger mode> : Trigger mode
-s <sample size> : Sample size to acquire (set to 0 to use memory depth as sample size)
-t <boolean condition> : Multiple trigger Boolean condition
-b <cable name/index> : Cable name or index
-d <device index> : Device index
add_trigger -n <clock domain id> -p <probe id> -s <signal name> ?-t <trigger type>? ?-e <trigger event>? ?-v <value>? ?-w <compare width>? ?-b <cable name/index>? ?-d <device index>? : To add a trigger configuration into a clock domain.
-n <clock domain id> : Clock domain ID
-p <probe id> : Probe ID
-s <signal name> : Signal name or index
-t <trigger type> : Trigger type
-e <trigger event> : Trigger event associated with the trigger type
-v <value> : Compare value
-w <compare width> : Compare value width (no. of bits)
-b <cable name/index> : Cable name or index
-d <device index> : Device index
edit_trigger -n <clock domain id> -i <index> -p <probe id> -s <signal name> ?-t <trigger type>? ?-e <trigger event>? ?-v <value>? ?-w <compare width>? ?-b <cable name/index>? ?-d <device index>? : To edit an existing trigger configuration of a clock domain.
-n <clock domain id> : Clock domain ID
-i <index> : Trigger entry index to modify
-p <probe id> : Probe ID
-s <signal name> : Signal name or index
-t <trigger type> : Trigger type
-e <trigger event> : Trigger event associated with the trigger type
-v <value> : Compare value
-w <compare width> : Compare value width (no. of bits)
-b <cable name/index> : Cable name or index
-d <device index> : Device index
remove_trigger -n <clock domain id> -i <index> ?-b <cable name/index>? ?-d <device index>? : To remove an existing trigger configuration from a clock domain.
-n <clock domain id> : Clock domain ID
-i <index> : Trigger entry index to remove
-b <cable name/index> : Cable name or index
-d <device index> : Device index
start -n <clock domain id> ?-b <cable name/index>? ?-d <device index>? ?-t <seconds>? ?-o <filepath>? : To start the OCLA debug subsystem of a clock domain to capture signal samples.
-n <clock domain id> : Clock domain ID
-b <cable name/index> : Cable name or index
-d <device index> : Device index
-t <seconds> : Command timeout in seconds (default 60)
-o <filepath> : Output waveform filepath
status -n <clock domain id> ?-b <cable name/index>? ?-d <device index>? : To query the clock domain sampling status.
-n <clock domain id> : Clock domain ID
-b <cable name/index> : Cable name or index
-d <device index> : Device index
show_waveform -n <clock domain id> ?-b <cable name/index>? ?-d <device index>? ?-o <filepath>? : To generate waveform file and display the signal waveform of a clock domain in GtkWave UI app.
-n <clock domain id> : Clock domain ID
-b <cable name/index> : Cable name or index
-d <device index> : Device index
-o <filepath> : Output waveform filepath
set_io ?-b <cable name/index>? ?-d <device index>? <signal1=value1> <signal2=value2> : To configure the state/value of an IO signal.
-b <cable name/index> : Cable name or index
-d <device index> : Device index
sig1=val1...sigN=valN : List of signal names or indexes and values to set
get_io ?-b <cable name/index>? ?-d <device index>? ?-l <times>? ?-t <milliseconds>? <signal1> <signal2> : To read the state/value of an IO signal.
-b <cable name/index> : Cable name or index
-d <device index> : Device index
sig1...sigN : List of signal names or indexes to read
--------------------
- Helper functions -
--------------------
get_design_name : Returns the design name
get_top_module : Returns the top module name
get_top_simulation_module : Returns the top simulation module name
get_design_files : Returns a list of all the design files
get_simulation_files : Returns a list of all the simulation files
get_bin_path : Returns the path to all Raptor binary executables
get_data_path : Returns the path to Raptor installed shared directory
get_python3_path : Returns the path to the Python 3 Raptor installed executable
message <message> : Prints a message
error_message <message> : Prints an error message and stops Tcl execution
-----------------------------------------------
Example designs are installed with Raptor under:
<install_path>/share/raptor/examples (ie: /usr/local/share/raptor/examples) for Project examples
and
<install_path>/share/raptor/tcl_examples (ie: /usr/local/share/raptor/tcl_examples) for Tcl examples
To run one of the examples, cd into any local user directory and run:
raptor --script $RAPTOR_PATH/share/raptor/tcl_examples/and2_verilog/raptor.tcl (GUI mode)
or
raptor --batch --script $RAPTOR_PATH/share/raptor/tcl_examples/and2_verilog/raptor.tcl (Batch mode)
A project directory gets created with all the artefacts generated by Raptor.
A log file gets created too: raptor.log with all the compilation steps logs agregated.
Example designs, please refer to:
<install_path>/share/raptor/tcl_examples/readme_raptor_examples.txt for a complete list of examples.
Each call to the "add_design_file" creates a separate Compilation Unit (In the Verilog sense),
the files in that call share the same macro definition space.
Verilog and VHDL files cannot be mixed in the same "add_design_file" call.
VHDL Libraries are not supported at this time, only individual .vhdl file compilation is.
A .sdc file (Tcl file with special handling of square brackets[]) can be provided using the "add_constraint_file" command.
The file and contain classic SDC commands, Tcl scripting and set_pin_loc commands.
SDC are honored by the Placement and STA stages.
Synthesis will preserve with best effort the names of the signals referenced in the contraints in order for the Placement and STA to find them in the netlist.
