Revert "Flatten wrapper after design editing"

os-fpga · Mar 27, 2024 · d05c0eb · d05c0eb
1 parent 2b9dd0d
commit d05c0eb
Showing 1 changed file with 3 additions and 6 deletions.
diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc
@@ -692,9 +692,8 @@ struct DesignEditRapidSilicon : public ScriptPass {
 
     wrapper_mod->fixup_ports();
 
-    new_design->add(wrapper_mod);
     new_design->add(interface_mod);
-    Pass::call(new_design, "flatten");
+    new_design->add(wrapper_mod);
 
     for (auto file : wrapper_files) {
       std::string extension = get_extension(file);
@@ -727,12 +726,10 @@ struct DesignEditRapidSilicon : public ScriptPass {
             {
               cell->unsetPort(portName);
               RTLIL::SigSpec conn = wire;
-              int width = wire->width;
-              for(int i=0; i<width; i++)
+              for(int i=0; i<wire->width; i++)
               {
                 IdString nportName = std::string(portName.c_str()) + "[" + std::to_string(i) + "]";
-                unsigned index = (wire->upto) ? (width - 1 - i) : i;
-                cell->setPort(nportName, conn[index]);
+                cell->setPort(nportName, conn[i]);
               }
             }
           }