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Raptor_Tools update
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@alaindargelas
alaindargelas committed Jan 18, 2024
1 parent f87e073 commit d0d67d4
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2 changes: 1 addition & 1 deletion Raptor_Tools
Submodule Raptor_Tools updated 43 files
+19 −0 Flex_LM/CMakeLists.txt
+163 −0 Flex_LM/License_manager.cpp
+86 −0 Flex_LM/License_manager.hpp
+6 −1 gatelevel_readers/reconstruct_verilog/run.sh
+2,489 −0 gatelevel_readers/reconstruct_verilog/src/reconstruct_dsp38.h
+464 −0 gatelevel_readers/reconstruct_verilog/src/reconstruct_ram18kx2.h
+599 −0 gatelevel_readers/reconstruct_verilog/src/reconstruct_ram36k.h
+35 −0 gatelevel_readers/reconstruct_verilog/src/reconstruct_utils.h
+1 −1 gatelevel_readers/reconstruct_verilog/src/reconstruct_verilog.cpp
+182 −2,669 gatelevel_readers/reconstruct_verilog/src/reconstruct_verilog.h
+706 −0 gatelevel_readers/reconstruct_verilog/src/transform_blif.h
+9 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/eblif/dsp19x2_to_rs_dsp_XX_mapping0001.eblif
+9 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/eblif/dsp19x2_to_rs_dsp_XX_mapping0010.eblif
+9 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/eblif/dsp19x2_to_rs_dsp_XX_mapping0011.eblif
+9 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/eblif/dsp19x2_to_rs_dsp_XX_mapping0100.eblif
+9 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/eblif/dsp19x2_to_rs_dsp_XX_mapping0101.eblif
+9 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/eblif/dsp19x2_to_rs_dsp_XX_mapping0110.eblif
+9 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/eblif/dsp19x2_to_rs_dsp_XX_mapping0111.eblif
+9 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/eblif/dsp19x2_to_rs_dsp_XX_mapping1000.eblif
+9 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/eblif/dsp19x2_to_rs_dsp_XX_mapping1001.eblif
+9 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/eblif/dsp19x2_to_rs_dsp_XX_mapping1010.eblif
+9 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/eblif/dsp19x2_to_rs_dsp_XX_mapping1011.eblif
+9 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/eblif/dsp19x2_to_rs_dsp_XX_mapping____.eblif
+582 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/json/orig/dsp19x2_to_rs_dsp_XX_mapping_____ports.json
+60 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/verilog/dsp19x2_to_rs_dsp_XX_mapping0001.v
+60 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/verilog/dsp19x2_to_rs_dsp_XX_mapping0010.v
+60 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/verilog/dsp19x2_to_rs_dsp_XX_mapping0011.v
+67 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/verilog/dsp19x2_to_rs_dsp_XX_mapping0100.v
+68 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/verilog/dsp19x2_to_rs_dsp_XX_mapping0101.v
+67 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/verilog/dsp19x2_to_rs_dsp_XX_mapping0110.v
+67 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/verilog/dsp19x2_to_rs_dsp_XX_mapping0111.v
+65 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/verilog/dsp19x2_to_rs_dsp_XX_mapping1000.v
+65 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/verilog/dsp19x2_to_rs_dsp_XX_mapping1001.v
+65 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/verilog/dsp19x2_to_rs_dsp_XX_mapping1010.v
+65 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/verilog/dsp19x2_to_rs_dsp_XX_mapping1011.v
+59 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/verilog/dsp19x2_to_rs_dsp_XX_mapping____.v
+291 −0 gatelevel_readers/reconstruct_verilog/tests/DSP19x2/verilog/orig/dsp19x2_to_rs_dsp_XX_mapping.v
+23 −0 gatelevel_readers/reconstruct_verilog/tests/RAM/TDP_RAM18KX2_primitive_inst_post_synth.eblif
+17 −0 gatelevel_readers/reconstruct_verilog/tests/RAM/TDP_RAM36K_primitive_inst_post_synth.eblif
+157 −0 gatelevel_readers/reconstruct_verilog/tests/RAM/golden/TDP_RAM18KX2_primitive_inst_post_synth_golden.eblif
+149 −0 gatelevel_readers/reconstruct_verilog/tests/RAM/golden/TDP_RAM36K_primitive_inst_post_synth_golden.eblif
+949 −0 ...evel_readers/reconstruct_verilog/tests/new_DSP38/golden/accum_output_registered_iverilog_post_rout_golden.v
+1 −1 gatelevel_readers/reconstruct_verilog/tests/new_DSP38/verilog/dsp38_sim_scratch.v

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