os-fpga · thierryBesson · Aug 2, 2023 · Aug 2, 2023 · Aug 2, 2023 · Aug 2, 2023
diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -14,7 +14,7 @@ endif(NOT CMAKE_BUILD_TYPE)
 
 set(VERSION_MAJOR 0)
 set(VERSION_MINOR 0)
-set(VERSION_PATCH 220)
+set(VERSION_PATCH 221)
 
 project(yosys_verific_rs)
 

diff --git a/RTL_Benchmark b/RTL_Benchmark
diff --git a/suites/yosys_validation/bram_valid.json b/suites/yosys_validation/bram_valid.json
@@ -7,6 +7,24 @@
     "num_process": 4,
     "timeout": 1800,
     "benchmarks": {
+        "EDA-1776": {
+            "compile_status" : "active",
+            "sim_status": "active",
+            "test_path": "RTL_Benchmark/Verilog/yosys_validation/EDA-1776/",
+            "top_module": "bytewrite_sp_ram_wf_block"
+        },
+        "EDA-1777": {
+            "compile_status" : "active",
+            "sim_status": "active",
+            "test_path": "RTL_Benchmark/Verilog/yosys_validation/EDA-1777/",
+            "top_module": "bytewrite_tdp_ram_wf"
+        },
+        "EDA-1587": {
+            "compile_status" : "active",
+            "sim_status": "active",
+            "test_path": "RTL_Benchmark/Verilog/yosys_validation/EDA-1587/",
+            "top_module": "axi_ram"
+        },
         "EDA-402-komal": {
             "compile_status" : "inactive",
             "sim_status": "inactive",

diff --git a/yosys b/yosys
diff --git a/yosys-rs-plugin b/yosys-rs-plugin