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EDA-3010/EDA-2953 updated fix #707

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merged 2 commits into from
Jul 4, 2024
Merged

EDA-3010/EDA-2953 updated fix #707

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e60d971
EDA-3010 updated fix
AYYAZmayo Jul 4, 2024
bc193e1
Fix,EDA-2953
AYYAZmayo Jul 4, 2024
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5 changes: 3 additions & 2 deletions design_edit/src/rs_design_edit.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -479,8 +479,9 @@ struct DesignEditRapidSilicon : public ScriptPass {
string module_name = remove_backslashes(cell->type.str());
if (std::find(primitives.begin(), primitives.end(), module_name) !=
primitives.end()) {
bool is_out_prim = (module_name.substr(0, 2) == "O_") ? true : false;
if (is_out_prim) continue;
//EDA-3010: output primitives cal also have danlging output wire
//bool is_out_prim = (module_name.substr(0, 2) == "O_") ? true : false;
//if (is_out_prim) continue;
// Upgrading dangling outs of input primtives to output ports
for (auto port : cell->connections()){
IdString portName = port.first;
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2 changes: 1 addition & 1 deletion yosys
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Submodule yosys updated 1 files
+38 −2 passes/techmap/clkbufmap.cc
2 changes: 1 addition & 1 deletion yosys-rs-plugin
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Submodule yosys-rs-plugin updated 3 files
+1 −0 Makefile
+224 −0 genesis3/gen3_techmap.v
+20 −1 src/synth_rapidsilicon.cc
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