Laboratory work for the first semester course on Computer Architecture, taught by P.S. Skakov at the CT Department of ITMO University.
You have to implement a counter and a linear feedback shift register using wires (better do this in the Logisim evolution application).
You have to implement a CPU cache in Verilog (System Verilog) language and describe the model with Java, Python or C++ (Read about a DDR memory).
You have to implement disassembler for basic commands (you can even avoid privileged commands) of RISC-V ISA. Don’t miss a couple of commands because they have tests for every command in the specification.
You have to implement parallel program on C++ using OpenMP. For high scores you have to achieve parallelism in Superscalar.
