Configure Clock

polesskiy-dev · Nov 19, 2023 · 92e71de · 92e71de
1 parent ceeec9c
commit 92e71de
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diff --git a/firmware/iot-risk-data-logger-nfc-samd21.X/iot-risk-data-logger-nfc-samd21.mc3 b/firmware/iot-risk-data-logger-nfc-samd21.X/iot-risk-data-logger-nfc-samd21.mc3
diff --git a/firmware/iot-risk-data-logger-nfc-samd21.X/nbproject/Makefile-genesis.properties b/firmware/iot-risk-data-logger-nfc-samd21.X/nbproject/Makefile-genesis.properties
@@ -1,5 +1,5 @@
 #
-#Sat Nov 18 16:53:24 TRT 2023
+#Sun Nov 19 19:46:27 TRT 2023
 default.languagetoolchain.version=4.35
 default.Pack.dfplocation=/Applications/microchip/mplabx/v6.15/packs/Microchip/SAMD21_DFP/3.6.144
 default.com-microchip-mplab-mdbcore-simulator-Simulator.md5=aa9d1097190a66d1314d421a6f2603b4

diff --git a/firmware/iot-risk-data-logger-nfc-samd21.X/nbproject/private/private.xml b/firmware/iot-risk-data-logger-nfc-samd21.X/nbproject/private/private.xml
@@ -1,6 +1,10 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <project-private xmlns="http://www.netbeans.org/ns/project-private/1">
+    <editor-bookmarks xmlns="http://www.netbeans.org/ns/editor-bookmarks/2" lastBookmarkId="0"/>
     <open-files xmlns="http://www.netbeans.org/ns/projectui-open-files/2">
-        <group/>
+        <group>
+            <file>file:/Users/artempolisskyi/projects/iot-risk-data-logger-nfc-samd21/firmware/src/config/default/usb_device_init_data.c</file>
+            <file>file:/Users/artempolisskyi/projects/iot-risk-data-logger-nfc-samd21/firmware/src/config/default/driver/memory/drv_memory.h</file>
+        </group>
     </open-files>
 </project-private>
diff --git a/firmware/src/config/default/FreeRTOSConfig.h b/firmware/src/config/default/FreeRTOSConfig.h
@@ -45,7 +45,7 @@
 #define configUSE_PREEMPTION                    1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
 #define configUSE_TICKLESS_IDLE                 0
-#define configCPU_CLOCK_HZ                      ( 48000000UL )
+#define configCPU_CLOCK_HZ                      ( 47972352UL )
 #define configTICK_RATE_HZ                      ( ( TickType_t ) 1000 )
 #define configMAX_PRIORITIES                    ( 5UL )
 #define configMINIMAL_STACK_SIZE                ( 128 )

diff --git a/firmware/src/config/default/configuration.h b/firmware/src/config/default/configuration.h
@@ -85,7 +85,7 @@ extern "C" {
 #define SYS_TIME_HW_COUNTER_WIDTH                   (16)
 #define SYS_TIME_HW_COUNTER_PERIOD                  (0xFFFFU)
 #define SYS_TIME_HW_COUNTER_HALF_PERIOD             (SYS_TIME_HW_COUNTER_PERIOD>>1)
-#define SYS_TIME_CPU_CLOCK_FREQUENCY                (48000000)
+#define SYS_TIME_CPU_CLOCK_FREQUENCY                (47972352)
 #define SYS_TIME_COMPARE_UPDATE_EXECUTION_CYCLES    (200)
 
 

diff --git a/firmware/src/config/default/definitions.h b/firmware/src/config/default/definitions.h
@@ -93,7 +93,7 @@ extern "C" {
 #define DEVICE_SERIES		 "SAMD21"
 
 /* CPU clock frequency */
-#define CPU_CLOCK_FREQUENCY 48000000
+#define CPU_CLOCK_FREQUENCY 47972352
 
 // *****************************************************************************
 // *****************************************************************************

diff --git a/firmware/src/config/default/harmony-manifest-success.yml b/firmware/src/config/default/harmony-manifest-success.yml
@@ -4,7 +4,7 @@
 
 
 project: iot-risk-data-logger-nfc-samd21
-creation_date: 2023-11-18T16:53:23.323+03:00[Europe/Istanbul]    # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime
+creation_date: 2023-11-19T19:46:26.009+03:00[Europe/Istanbul]    # ISO 8601 format: https://www.w3.org/TR/NOTE-datetime
 operating_system: Mac OS X
 mcc_mode: IDE            # [IDE|Standalone|Headless]
 mcc_version: v5.3.7

diff --git a/firmware/src/config/default/library/cryptoauthlib/hal/hal_cortex_m_delay.c b/firmware/src/config/default/library/cryptoauthlib/hal/hal_cortex_m_delay.c
@@ -34,7 +34,7 @@
 #include <stdint.h>
 
 #ifndef CONF_CPU_FREQUENCY
-#define CONF_CPU_FREQUENCY 48000000
+#define CONF_CPU_FREQUENCY 47972352
 #endif
 
 #if CONF_CPU_FREQUENCY < 1000

diff --git a/firmware/src/config/default/peripheral/clock/plib_clock.c b/firmware/src/config/default/peripheral/clock/plib_clock.c
@@ -44,6 +44,15 @@
 
 static void SYSCTRL_Initialize(void)
 {
+    /****************** XOSC32K initialization  ******************************/
+
+    /* Configure 32K External Oscillator */
+    SYSCTRL_REGS->SYSCTRL_XOSC32K = SYSCTRL_XOSC32K_STARTUP(0U) | SYSCTRL_XOSC32K_ENABLE_Msk | SYSCTRL_XOSC32K_RUNSTDBY_Msk | SYSCTRL_XOSC32K_EN32K_Msk | SYSCTRL_XOSC32K_XTALEN_Msk;
+    while(!((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_XOSC32KRDY_Msk) == SYSCTRL_PCLKSR_XOSC32KRDY_Msk))
+    {
+        /* Waiting for the XOSC32K Ready state */
+    }
+
     SYSCTRL_REGS->SYSCTRL_OSC32K = 0x0U;
 }
 
@@ -64,17 +73,24 @@ static void DFLL_Initialize(void)
 
     SYSCTRL_REGS->SYSCTRL_DFLLVAL = SYSCTRL_DFLLVAL_COARSE(calibCoarse) | SYSCTRL_DFLLVAL_FINE(512U);
 
+    GCLK_REGS->GCLK_CLKCTRL = GCLK_CLKCTRL_GEN(0x2U)  | GCLK_CLKCTRL_CLKEN_Msk | GCLK_CLKCTRL_ID(0U);
+    while((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_DFLLRDY_Msk) != SYSCTRL_PCLKSR_DFLLRDY_Msk)
+    {
+        /* Waiting for the Ready state */
+    }
+    SYSCTRL_REGS->SYSCTRL_DFLLMUL = SYSCTRL_DFLLMUL_MUL(1464U) | SYSCTRL_DFLLMUL_FSTEP(1U) | SYSCTRL_DFLLMUL_CSTEP(1U);
+
     while((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_DFLLRDY_Msk) != SYSCTRL_PCLKSR_DFLLRDY_Msk)
     {
         /* Waiting for the Ready state */
     }
 
     /* Configure DFLL    */
-    SYSCTRL_REGS->SYSCTRL_DFLLCTRL = SYSCTRL_DFLLCTRL_ENABLE_Msk ;
+    SYSCTRL_REGS->SYSCTRL_DFLLCTRL = SYSCTRL_DFLLCTRL_ENABLE_Msk | SYSCTRL_DFLLCTRL_MODE_Msk ;
 
-    while((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_DFLLRDY_Msk) != SYSCTRL_PCLKSR_DFLLRDY_Msk)
+    while((SYSCTRL_REGS->SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_DFLLLCKF_Msk) != SYSCTRL_PCLKSR_DFLLLCKF_Msk)
     {
-        /* Waiting for DFLL to be ready */
+        /* Waiting for DFLL to fully lock to meet clock accuracy */
     }
 
 }
@@ -92,6 +108,29 @@ static void GCLK0_Initialize(void)
 }
 
 
+static void GCLK1_Initialize(void)
+{
+    GCLK_REGS->GCLK_GENCTRL = GCLK_GENCTRL_SRC(5U) | GCLK_GENCTRL_RUNSTDBY_Msk | GCLK_GENCTRL_GENEN_Msk | GCLK_GENCTRL_ID(1U);
+
+    GCLK_REGS->GCLK_GENDIV = GCLK_GENDIV_DIV(32U) | GCLK_GENDIV_ID(1U);
+    while((GCLK_REGS->GCLK_STATUS & GCLK_STATUS_SYNCBUSY_Msk) == GCLK_STATUS_SYNCBUSY_Msk)
+    {
+        /* wait for the Generator 1 synchronization */
+    }
+}
+
+
+static void GCLK2_Initialize(void)
+{
+    GCLK_REGS->GCLK_GENCTRL = GCLK_GENCTRL_SRC(5U) | GCLK_GENCTRL_GENEN_Msk | GCLK_GENCTRL_ID(2U);
+
+    while((GCLK_REGS->GCLK_STATUS & GCLK_STATUS_SYNCBUSY_Msk) == GCLK_STATUS_SYNCBUSY_Msk)
+    {
+        /* wait for the Generator 2 synchronization */
+    }
+}
+
+
 
 
 
@@ -100,12 +139,14 @@ void CLOCK_Initialize (void)
     /* Function to Initialize the Oscillators */
     SYSCTRL_Initialize();
 
+    GCLK1_Initialize();
+    GCLK2_Initialize();
     DFLL_Initialize();
     GCLK0_Initialize();
 
 
     /* Selection of the Generator and write Lock for RTC */
-    GCLK_REGS->GCLK_CLKCTRL = GCLK_CLKCTRL_ID(4U) | GCLK_CLKCTRL_GEN(0x0U)  | GCLK_CLKCTRL_CLKEN_Msk;
+    GCLK_REGS->GCLK_CLKCTRL = GCLK_CLKCTRL_ID(4U) | GCLK_CLKCTRL_GEN(0x1U)  | GCLK_CLKCTRL_CLKEN_Msk;
     /* Selection of the Generator and write Lock for EIC */
     GCLK_REGS->GCLK_CLKCTRL = GCLK_CLKCTRL_ID(5U) | GCLK_CLKCTRL_GEN(0x0U)  | GCLK_CLKCTRL_CLKEN_Msk;
     /* Selection of the Generator and write Lock for USB */

diff --git a/firmware/src/config/default/peripheral/rtc/plib_rtc.h b/firmware/src/config/default/peripheral/rtc/plib_rtc.h
@@ -55,7 +55,7 @@ extern "C" {
 // DOM-IGNORE-END
 
 /* Frequency of Counter Clock for RTC */
-#define RTC_COUNTER_CLOCK_FREQUENCY        (48000000U / (1UL << (0x0U)))
+#define RTC_COUNTER_CLOCK_FREQUENCY        (1024U / (1UL << (0x0U)))
 
 typedef enum
 {

diff --git a/firmware/src/config/default/peripheral/sercom/i2c_master/plib_sercom0_i2c_master.c b/firmware/src/config/default/peripheral/sercom/i2c_master/plib_sercom0_i2c_master.c
@@ -202,7 +202,7 @@ bool SERCOM0_I2C_TransferSetup(SERCOM_I2C_TRANSFER_SETUP* setup, uint32_t srcClk
 
     if( srcClkFreq == 0U)
     {
-        srcClkFreq = 48000000UL;
+        srcClkFreq = 47972352UL;
     }
 
     if (SERCOM0_I2C_CalculateBaudValue(srcClkFreq, i2cClkSpeed, &baudValue) == false)

diff --git a/firmware/src/config/default/peripheral/sercom/spi_master/plib_sercom1_spi_master.c b/firmware/src/config/default/peripheral/sercom/spi_master/plib_sercom1_spi_master.c
@@ -56,10 +56,10 @@
 
 
 /* SERCOM1 clk freq value for the baud calculation */
-#define SERCOM1_Frequency      (48000000UL)
+#define SERCOM1_Frequency      (47972352UL)
 
 /* SERCOM1 SPI baud value for 1000000 Hz baud rate */
-#define SERCOM1_SPIM_BAUD_VALUE         (23UL)
+#define SERCOM1_SPIM_BAUD_VALUE         (22UL)
 
 /*Global object to save SPI Exchange related data  */
 volatile static SPI_OBJECT sercom1SPIObj;

diff --git a/firmware/src/config/default/peripheral/tc/plib_tc3.c b/firmware/src/config/default/peripheral/tc/plib_tc3.c
@@ -87,7 +87,7 @@ void TC3_TimerInitialize( void )
     TC3_REGS->COUNT16.TC_CTRLA = TC_CTRLA_MODE_COUNT16 | TC_CTRLA_PRESCALER_DIV1 | TC_CTRLA_WAVEGEN_MPWM ;
 
     /* Configure timer period */
-    TC3_REGS->COUNT16.TC_CC[0U] = 47999U;
+    TC3_REGS->COUNT16.TC_CC[0U] = 47971U;
 
     /* Clear all interrupt flags */
     TC3_REGS->COUNT16.TC_INTFLAG = TC_INTFLAG_Msk;
@@ -125,7 +125,7 @@ void TC3_TimerStop( void )
 
 uint32_t TC3_TimerFrequencyGet( void )
 {
-    return (uint32_t)(48000000UL);
+    return (uint32_t)(47972352UL);
 }
 
 void TC3_TimerCommandSet(TC_COMMAND command)