Skip to content

Commit

Permalink
Some more bunch of changes:
Browse files Browse the repository at this point in the history 
    - Add options to config script
    - Set request size for node and tag controllers
    - Modify ld/st insn behaviour to clear the tag on a scalar value

Change-Id: I207b45eb6978707c05b3ea5ab8e0babf9df26d1a
  • Loading branch information
@hakase56557
hakase56557 committed Jun 30, 2023
1 parent 9eef782 commit 4062809
Show file tree
Hide file tree
Showing 7 changed files with 103 additions and 63 deletions.
18 changes: 14 additions & 4 deletions configs/capstone/fast-forward.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,8 @@
parser.add_argument('--cpu', type=str, default='simple', help='CPU model (atomic, simple, o3)')
parser.add_argument('--mocktag', action='store_true', help='use mock tag')
parser.add_argument('--ckpt', type=str, default ='', help='restore checkpoint from here')
parser.add_argument('--tcache-memside', type=str, default ='l2', help='tcache mem side connection')
parser.add_argument('--ckpt-save', type=str, default ='m5out/ckp', help='checkpoint save directory')

if '--' not in sys.argv:
sys.stderr.write('Usage: fast-forward.py [flags] -- <commands>')
Expand Down Expand Up @@ -56,9 +58,11 @@ class L1Cache(Cache):

class L1ICache(L1Cache):
size = '16kB'
# prefetcher = TaggedPrefetcher(degree=1, prefetch_on_access=True)

class L1DCache(L1Cache):
size = '64kB'
# prefetcher = TaggedPrefetcher(degree=1, prefetch_on_access=True)

class NCache(Cache):
size = args.ncache_size
Expand All @@ -68,6 +72,7 @@ class NCache(Cache):
response_latency = 2
mshrs = 4
tgts_per_mshr = 20
# prefetcher = TaggedPrefetcher(degree=1, prefetch_on_access=True)

class TCache(Cache):
size = args.tcache_size
Expand All @@ -77,16 +82,19 @@ class TCache(Cache):
response_latency = 2
mshrs = 4
tgts_per_mshr = 20
prefetcher = TaggedPrefetcher(degree=1, prefetch_on_access=True)


class L2Cache(Cache):
size = '256kB'
# size = '1024kB'
assoc = 8
tag_latency = 20
data_latency = 20
response_latency = 20
mshrs = 20
tgts_per_mshr = 12
# prefetcher = TaggedPrefetcher(degree=1, prefetch_on_access=True)

system = System()

Expand All @@ -113,7 +121,10 @@ class L2Cache(Cache):
if 'tcache_port' in system.cpu._ports and not args.mocktag:
system.cpu.tcache = TCache()
system.cpu.tcache_port = system.cpu.tcache.cpu_side
system.cpu.tcache.mem_side = system.l2bus.cpu_side_ports
if args.tcache_memside == 'l2':
system.cpu.tcache.mem_side = system.l2bus.cpu_side_ports
else:
system.cpu.tcache.mem_side = system.membus.cpu_side_ports

system.l2bus.mem_side_ports = system.l2cache.cpu_side
system.l2cache.mem_side = system.membus.cpu_side_ports
Expand Down Expand Up @@ -203,9 +214,8 @@ class L2Cache(Cache):
.format(m5.curTick(), exit_event.getCause()))

if exit_event.getCause() == 'checkpoint':
m5.checkpoint('m5out/ckp')

if exit_event.getCause() == 'm5_exit instruction encountered':
m5.checkpoint(args.ckpt_save)
while exit_event.getCause() == 'm5_exit instruction encountered':
m5.stats.reset()
#m5.stats.dump()
exit_event = m5.simulate()
Expand Down
125 changes: 71 additions & 54 deletions src/arch/riscvcapstone/isa/decoder.isa
View file
Original file line number Diff line number Diff line change
Expand Up @@ -631,7 +631,7 @@ decode QUADRANT default Unknown::unknown() {
}});
}
format RNodeMemOp {
0xe: lwc ({{
0xe: ldc ({{
Rd_trv; Rs1_trv;

assert(Rs1_trv.getTag());
Expand Down Expand Up @@ -698,7 +698,7 @@ decode QUADRANT default Unknown::unknown() {

Rd_trv = Rd_trv;
}});
0x13: lws ({{
0x13: lts ({{
Rd_trv; Rs1_trv;

assert(Rs1_trv.getTag());
Expand Down Expand Up @@ -741,7 +741,7 @@ decode QUADRANT default Unknown::unknown() {

Rd_trv = Rd_trv;
}});
0x16: lbs ({{
0x16: ldb ({{
Rd_trv; Rs1_trv;

assert(Rs1_trv.getTag());
Expand All @@ -751,12 +751,16 @@ decode QUADRANT default Unknown::unknown() {
}}, {{
Addr EA = Rs1_trv.getRegVal().capVal().cursor();

if(EA + sizeof(uint8_t) > Rs1_trv.getRegVal().capVal().end())
return std::make_shared<IllegalInstFault>(
"Illegal read - out of capability bounds!", machInst);

Addr alignment = EA & (sizeof(RegVal) - 1);
dyn_inst->initiateSetTag((EA - alignment), false);

//TODO: retrieve tag bit to make sure it corresponds
//with the called inst?

DPRINTFN("MemReads count = %d, tag query count = %d\n",
dyn_inst->memReadN, dyn_inst->tagQueryN);

//TODO: Maybe separate these statements
//and introduce a new type(s) of fault
if (static_cast<int>(Rs1_trv.getRegVal().capVal().perm()) < 1 ||
Expand All @@ -767,9 +771,6 @@ decode QUADRANT default Unknown::unknown() {
return std::make_shared<IllegalInstFault>(
"Rs1 doesn't have the necessary perms", machInst);
}}, {{
//Addr alignment = EA & (sizeof(RegVal) - 1);
//dyn_inst->initiateSetTag((EA - alignment), false);

uint8_t& cap = Mem_ub;

getMemLE(pkt, cap, traceData);
Expand All @@ -780,7 +781,7 @@ decode QUADRANT default Unknown::unknown() {

Rd_trv = Rd_trv;
}});
0x17: lhs ({{
0x17: ldd ({{
Rd_trv; Rs1_trv;

assert(Rs1_trv.getTag());
Expand All @@ -794,12 +795,12 @@ decode QUADRANT default Unknown::unknown() {
return std::make_shared<IllegalInstFault>(
"Illegal read - out of capability bounds!", machInst);

Addr alignment = EA & (sizeof(RegVal) - 1);
dyn_inst->initiateSetTag((EA - alignment), false);

//TODO: retrieve tag bit to make sure it corresponds
//with the called inst?

DPRINTFN("MemReads count = %d, tag query count = %d\n",
dyn_inst->memReadN, dyn_inst->tagQueryN);

//TODO: Maybe separate these statements
//and introduce a new type(s) of fault
if (static_cast<int>(Rs1_trv.getRegVal().capVal().perm()) < 1 ||
Expand All @@ -820,7 +821,7 @@ decode QUADRANT default Unknown::unknown() {

Rd_trv = Rd_trv;
}});
0x18: l16s ({{
0x18: ldh ({{
Rd_trv; Rs1_trv;

assert(Rs1_trv.getTag());
Expand All @@ -834,12 +835,12 @@ decode QUADRANT default Unknown::unknown() {
return std::make_shared<IllegalInstFault>(
"Illegal read - out of capability bounds!", machInst);

Addr alignment = EA & (sizeof(RegVal) - 1);
dyn_inst->initiateSetTag((EA - alignment), false);

//TODO: retrieve tag bit to make sure it corresponds
//with the called inst?

//DPRINTFN("MemReads count = %d, tag query count = %d\n",
// dyn_inst->memReadN, dyn_inst->tagQueryN);

//TODO: Maybe separate these statements
//and introduce a new type(s) of fault
if (static_cast<int>(Rs1_trv.getRegVal().capVal().perm()) < 1 ||
Expand All @@ -860,7 +861,7 @@ decode QUADRANT default Unknown::unknown() {

Rd_trv = Rd_trv;
}});
0x19: l32s ({{
0x19: ldw ({{
Rd_trv; Rs1_trv;

assert(Rs1_trv.getTag());
Expand All @@ -874,12 +875,12 @@ decode QUADRANT default Unknown::unknown() {
return std::make_shared<IllegalInstFault>(
"Illegal read - out of capability bounds!", machInst);

Addr alignment = EA & (sizeof(RegVal) - 1);
dyn_inst->initiateSetTag((EA - alignment), false);

//TODO: retrieve tag bit to make sure it corresponds
//with the called inst?

DPRINTFN("MemReads count = %d, tag query count = %d\n",
dyn_inst->memReadN, dyn_inst->tagQueryN);

//TODO: Maybe separate these statements
//and introduce a new type(s) of fault
if (static_cast<int>(Rs1_trv.getRegVal().capVal().perm()) < 1 ||
Expand All @@ -902,7 +903,7 @@ decode QUADRANT default Unknown::unknown() {
}});
}
format RNodeStoreMemOp {
0xf: swc ({{ // check_code
0xf: stc ({{ // check_code
Rd_trv; Rs1_trv;

assert(Rd_trv.getTag());
Expand Down Expand Up @@ -948,7 +949,7 @@ decode QUADRANT default Unknown::unknown() {
Rd_trv = Rd_trv;
Rs1_trv = Rs1_trv;
}}, IsStore);
0x1d: sbc ({{ // check_code
0x1d: stb ({{ // check_code
Rd_trv; Rs1_trv;

assert(Rd_trv.getTag());
Expand All @@ -967,13 +968,16 @@ decode QUADRANT default Unknown::unknown() {
return std::make_shared<IllegalInstFault>(
"Illegal write - out of capability bounds!", machInst);

Addr alignment = EA & (sizeof(RegVal) - 1);
dyn_inst->initiateSetTag((EA - alignment), false);

Mem_ub = Rs1_trv.getRegVal().capVal().cursor();

Fault fault = dyn_inst->initiateGetTag(EA);
if(fault != NoFault)
return fault;
//Fault fault = dyn_inst->initiateGetTag(EA);
//if(fault != NoFault)
// return fault;

fault = writeMemTimingLE(xc, traceData, Mem_ub, EA,
Fault fault = writeMemTimingLE(xc, traceData, Mem_ub, EA,
memAccessFlags, nullptr);
if (fault != NoFault)
return fault;
Expand All @@ -984,17 +988,17 @@ decode QUADRANT default Unknown::unknown() {

Addr EA = rdv.capVal().cursor();

dyn_inst->initiateSetTag(EA, Rs1_trv.getTag());
if(Rs1_trv.getTag() && Rs1_trv.getRegVal().capVal().type() != CapType::NONLIN)
Rs1_trv.setTag(false);
//dyn_inst->initiateSetTag(EA, Rs1_trv.getTag());
//if(Rs1_trv.getTag() && Rs1_trv.getRegVal().capVal().type() != CapType::NONLIN)
Rs1_trv.setTag(false);

if(rdv.capVal().type() == CapType::UNINIT)
rdv.capVal().setCursor(EA + sizeof(uint8_t));

Rd_trv = Rd_trv;
Rs1_trv = Rs1_trv;
}}, IsStore);
0x1c: shc ({{ // check_code
0x1c: std ({{ // check_code
Rd_trv; Rs1_trv;

assert(Rd_trv.getTag());
Expand All @@ -1013,13 +1017,16 @@ decode QUADRANT default Unknown::unknown() {
return std::make_shared<IllegalInstFault>(
"Illegal write - out of capability bounds!", machInst);

Addr alignment = EA & (sizeof(RegVal) - 1);
dyn_inst->initiateSetTag((EA - alignment), false);

Mem_ud = Rs1_trv.getRegVal().capVal().cursor();

Fault fault = dyn_inst->initiateGetTag(EA);
if(fault != NoFault)
return fault;
//Fault fault = dyn_inst->initiateGetTag(EA);
//if(fault != NoFault)
// return fault;

fault = writeMemTimingLE(xc, traceData, Mem_ud, EA,
Fault fault = writeMemTimingLE(xc, traceData, Mem_ud, EA,
memAccessFlags, nullptr);
if (fault != NoFault)
return fault;
Expand All @@ -1030,17 +1037,17 @@ decode QUADRANT default Unknown::unknown() {

Addr EA = rdv.capVal().cursor();

dyn_inst->initiateSetTag(EA, Rs1_trv.getTag());
if(Rs1_trv.getTag() && Rs1_trv.getRegVal().capVal().type() != CapType::NONLIN)
Rs1_trv.setTag(false);
//dyn_inst->initiateSetTag(EA, Rs1_trv.getTag());
//if(Rs1_trv.getTag() && Rs1_trv.getRegVal().capVal().type() != CapType::NONLIN)
Rs1_trv.setTag(false);

if(rdv.capVal().type() == CapType::UNINIT)
rdv.capVal().setCursor(EA + sizeof(uint64_t));

Rd_trv = Rd_trv;
Rs1_trv = Rs1_trv;
}}, IsStore);
0x1a: s16c ({{ // check_code
0x1a: sth ({{ // check_code
Rd_trv; Rs1_trv;

assert(Rd_trv.getTag());
Expand All @@ -1059,13 +1066,16 @@ decode QUADRANT default Unknown::unknown() {
return std::make_shared<IllegalInstFault>(
"Illegal write - out of capability bounds!", machInst);

Addr alignment = EA & (sizeof(RegVal) - 1);
dyn_inst->initiateSetTag((EA - alignment), false);

Mem_uh = Rs1_trv.getRegVal().capVal().cursor();

Fault fault = dyn_inst->initiateGetTag(EA);
if(fault != NoFault)
return fault;
//Fault fault = dyn_inst->initiateGetTag(EA);
//if(fault != NoFault)
// return fault;

fault = writeMemTimingLE(xc, traceData, Mem_uh, EA,
Fault fault = writeMemTimingLE(xc, traceData, Mem_uh, EA,
memAccessFlags, nullptr);
if (fault != NoFault)
return fault;
Expand All @@ -1076,17 +1086,17 @@ decode QUADRANT default Unknown::unknown() {

Addr EA = rdv.capVal().cursor();

dyn_inst->initiateSetTag(EA, Rs1_trv.getTag());
if(Rs1_trv.getTag() && Rs1_trv.getRegVal().capVal().type() != CapType::NONLIN)
Rs1_trv.setTag(false);
//dyn_inst->initiateSetTag(EA, Rs1_trv.getTag());
//if(Rs1_trv.getTag() && Rs1_trv.getRegVal().capVal().type() != CapType::NONLIN)
Rs1_trv.setTag(false);

if(rdv.capVal().type() == CapType::UNINIT)
rdv.capVal().setCursor(EA + sizeof(uint16_t));

Rd_trv = Rd_trv;
Rs1_trv = Rs1_trv;
}}, IsStore);
0x1b: s32c ({{ // check_code
0x1b: stw ({{ // check_code
Rd_trv; Rs1_trv;

assert(Rd_trv.getTag());
Expand All @@ -1105,13 +1115,16 @@ decode QUADRANT default Unknown::unknown() {
return std::make_shared<IllegalInstFault>(
"Illegal write - out of capability bounds!", machInst);

Addr alignment = EA & (sizeof(RegVal) - 1);
dyn_inst->initiateSetTag((EA - alignment), false);

Mem_uw = Rs1_trv.getRegVal().capVal().cursor();

Fault fault = dyn_inst->initiateGetTag(EA);
if(fault != NoFault)
return fault;
//Fault fault = dyn_inst->initiateGetTag(EA);
//if(fault != NoFault)
// return fault;

fault = writeMemTimingLE(xc, traceData, Mem_uw, EA,
Fault fault = writeMemTimingLE(xc, traceData, Mem_uw, EA,
memAccessFlags, nullptr);
if (fault != NoFault)
return fault;
Expand All @@ -1122,9 +1135,9 @@ decode QUADRANT default Unknown::unknown() {

Addr EA = rdv.capVal().cursor();

dyn_inst->initiateSetTag(EA, Rs1_trv.getTag());
if(Rs1_trv.getTag() && Rs1_trv.getRegVal().capVal().type() != CapType::NONLIN)
Rs1_trv.setTag(false);
//dyn_inst->initiateSetTag(EA, Rs1_trv.getTag());
//if(Rs1_trv.getTag() && Rs1_trv.getRegVal().capVal().type() != CapType::NONLIN)
Rs1_trv.setTag(false);

if(rdv.capVal().type() == CapType::UNINIT)
rdv.capVal().setCursor(EA + sizeof(uint32_t));
Expand Down Expand Up @@ -1297,6 +1310,10 @@ decode QUADRANT default Unknown::unknown() {
assert(dyn_inst);
dyn_inst->printRegs();
}}, IsSerializing, IsNonSpeculative);
0xe: getrand ({{
srand(time(NULL));
Rd = (rand() % (Rs2 - Rs1) + Rs1) & 0xFFFFFFFFFFFFFFF0;
}});
}
format TagAccessStore {
0xb: tagset ({{
Expand Down
Loading

0 comments on commit 4062809

Please sign in to comment.