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#10 store: update refcount of capability at clen aligned PA
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@hakase56557
hakase56557 committed Sep 8, 2023
1 parent ee6488f commit 8bdde73
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Showing 2 changed files with 29 additions and 78 deletions.
75 changes: 1 addition & 74 deletions src/arch/riscvcapstone/isa/decoder.isa
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1272,27 +1272,14 @@ decode QUADRANT default Unknown::unknown() {
"Unexpected operand type (24)", machInst);
}
}}, {{ //memacc_code
static_assert(sizeof(RegVal) == 16);

Mem_rv = Rs2_trv.getRegVal();

//Fault fault = dyn_inst->initiateGetTag(EA);
//if(fault != NoFault)
// return fault;

Fault fault = writeMemTimingLE(xc, traceData, Mem.rawCapVal(), EA,
memAccessFlags, nullptr);
if (fault != NoFault)
return fault;
}}, {{ //comp_code
if(Rs1_trv.getTag()) {
Cap rs1_cap = Rs1_trv.getRegVal().capVal();

if(rs1_cap.type() == CapType::UNINIT)
rs1_cap.setCursor(rs1_cap.cursor() + sizeof(RegVal));

Rs1_trv.getRegVal().rawCapVal() = (uint128_t)rs1_cap;
}
//todo: optimization: update loaded cap refcount only if nodeid != Rs2.nodeid

if(Rs2_trv.getRegVal().capVal().type() != CapType::NONLIN)
Rs2_trv.setTag(false);
Expand Down Expand Up @@ -1745,28 +1732,13 @@ decode QUADRANT default Unknown::unknown() {
"Unexpected operand type (24)", machInst);
}
}}, {{ //memacc_code
Addr cap_aligned = EA & ~(sizeof(RegVal) - 1);
dyn_inst->initiateSetTag(cap_aligned, false);

Mem_sb = Rs2_trv.getRegVal().intVal();

//Fault fault = dyn_inst->initiateGetTag(EA);
//if(fault != NoFault)
// return fault;

Fault fault = writeMemTimingLE(xc, traceData, Mem_sb, EA,
memAccessFlags, nullptr);
if (fault != NoFault)
return fault;
}}, {{ // comp_code
if(Rs1_trv.getTag()) {
Cap rs1_cap = Rs1_trv.getRegVal().capVal();

if(rs1_cap.type() == CapType::UNINIT)
rs1_cap.setCursor(rs1_cap.cursor() + sizeof(Mem_sb));

Rs1_trv.getRegVal().rawCapVal() = (uint128_t)rs1_cap;
}
Rs1_trv = Rs1_trv;
}}, IsStore);
0x1: sh ({{ //check_code
Expand All @@ -1775,28 +1747,13 @@ decode QUADRANT default Unknown::unknown() {
"Unexpected operand type (24)", machInst);
}
}}, {{ //memacc_code
Addr cap_aligned = EA & ~(sizeof(RegVal) - 1);
dyn_inst->initiateSetTag(cap_aligned, false);

Mem_sh = Rs2_trv.getRegVal().intVal();

//Fault fault = dyn_inst->initiateGetTag(EA);
//if(fault != NoFault)
// return fault;

Fault fault = writeMemTimingLE(xc, traceData, Mem_sh, EA,
memAccessFlags, nullptr);
if (fault != NoFault)
return fault;
}}, {{ // comp_code
if(Rs1_trv.getTag()) {
Cap rs1_cap = Rs1_trv.getRegVal().capVal();

if(rs1_cap.type() == CapType::UNINIT)
rs1_cap.setCursor(rs1_cap.cursor() + sizeof(Mem_sh));

Rs1_trv.getRegVal().rawCapVal() = (uint128_t)rs1_cap;
}
Rs1_trv = Rs1_trv;
}}, IsStore);
0x2: sw ({{ //check_code
Expand All @@ -1805,28 +1762,13 @@ decode QUADRANT default Unknown::unknown() {
"Unexpected operand type (24)", machInst);
}
}}, {{ //memacc_code
Addr cap_aligned = EA & ~(sizeof(RegVal) - 1);
dyn_inst->initiateSetTag(cap_aligned, false);

Mem_sw = Rs2_trv.getRegVal().intVal();

//Fault fault = dyn_inst->initiateGetTag(EA);
//if(fault != NoFault)
// return fault;

Fault fault = writeMemTimingLE(xc, traceData, Mem_sw, EA,
memAccessFlags, nullptr);
if (fault != NoFault)
return fault;
}}, {{ // comp_code
if(Rs1_trv.getTag()) {
Cap rs1_cap = Rs1_trv.getRegVal().capVal();

if(rs1_cap.type() == CapType::UNINIT)
rs1_cap.setCursor(rs1_cap.cursor() + sizeof(Mem_sw));

Rs1_trv.getRegVal().rawCapVal() = (uint128_t)rs1_cap;
}
Rs1_trv = Rs1_trv;
}}, IsStore);
0x3: sd ({{ //check_code
Expand All @@ -1835,28 +1777,13 @@ decode QUADRANT default Unknown::unknown() {
"Unexpected operand type (24)", machInst);
}
}}, {{ //memacc_code
Addr cap_aligned = EA & ~(sizeof(RegVal) - 1);
dyn_inst->initiateSetTag(cap_aligned, false);

Mem_sd = Rs2_trv.getRegVal().intVal();

//Fault fault = dyn_inst->initiateGetTag(EA);
//if(fault != NoFault)
// return fault;

Fault fault = writeMemTimingLE(xc, traceData, Mem_sd, EA,
memAccessFlags, nullptr);
if (fault != NoFault)
return fault;
}}, {{ // comp_code
if(Rs1_trv.getTag()) {
Cap rs1_cap = Rs1_trv.getRegVal().capVal();

if(rs1_cap.type() == CapType::UNINIT)
rs1_cap.setCursor(rs1_cap.cursor() + sizeof(Mem_sd));

Rs1_trv.getRegVal().rawCapVal() = (uint128_t)rs1_cap;
}
Rs1_trv = Rs1_trv;
}}, IsStore);
}
Expand Down
32 changes: 28 additions & 4 deletions src/arch/riscvcapstone/isa/formats/rnode.isa
View file
Original file line number Diff line number Diff line change
Expand Up @@ -318,6 +318,9 @@ def template RNodeStoreExecute {{
return std::make_shared<IllegalInstFault>(
"Capability out of bound (28)", machInst);
}

NodeID node_id = rs1_cap.nodeId();
dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
} else {
EA = Rs1.getRegVal().intVal() + offset;

Expand All @@ -331,10 +334,13 @@ def template RNodeStoreExecute {{
return std::make_shared<IllegalInstFault>(
"Store address misaligned (6)", machInst);

if(cwrld || (!cwrld && emode)) {
NodeID node_id = rs1_cap.nodeId();
dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
}
Addr clen_aligned = EA & (sizeof(RegVal) - 1);
dyn_inst->initiateGetTag(clen_aligned);
RegVal dummy;
initiateMemRead(xc, traceData, clen_aligned, dummy, memAccessFlags);

//probably need to move this to comp_code if it breaks things
dyn_inst->initiateSetTag(clen_aligned, Rs2.getTag());

%(memacc_code)s;

Expand All @@ -354,6 +360,24 @@ def template RNodeStoreMemCompleteAcc {{
%(op_decl)s;
%(op_rd)s;

uint128_t cap_load;

if(dyn_inst->getTagQueryRes(0)) {
memcpy(&cap_load, dyn_inst->getMemReadRes(0), sizeof(cap_load));
Cap* cap = new Cap(cap_load);
NodeID node_id = cap->nodeId();
dyn_inst->initiateNodeCommand(new NodeRcUpdate(node_id, -1));
}

if(Rs1.getTag()) {
Cap rs1_cap = Rs1.getRegVal().capVal();

if(rs1_cap.type() == CapType::UNINIT)
rs1_cap.setCursor(rs1_cap.cursor() + sizeof(Mem));

Rs1.getRegVal().rawCapVal() = (uint128_t)rs1_cap;
}

%(comp_code)s;

%(op_wb)s;
Expand Down

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