Fix translation and node command issue for init cap

Change-Id: I04a7d88402af91fdbbb460bf3300b467044d032c
project-starch · Sep 21, 2023 · 9187a2d · 9187a2d
1 parent a725b76
commit 9187a2d
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Showing 4 changed files with 52 additions and 35 deletions.
diff --git a/src/arch/riscvcapstone/o3/cpu.cc b/src/arch/riscvcapstone/o3/cpu.cc
@@ -572,7 +572,7 @@ CPU::startup()
         ctrv.getRegVal().rawCapVal() = (uint128_t)*cap;
         isa[tid]->setTaggedMiscReg(1, ctrv); //capmiscreg_cinit
 
-        cwrld[tid] = 0;
+        cwrld[tid] = 1;
     }
 }
 

diff --git a/src/arch/riscvcapstone/o3/lsq.cc b/src/arch/riscvcapstone/o3/lsq.cc
@@ -848,42 +848,44 @@ LSQ::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
     request->initiateTranslation();
 
     /* This is the place were instructions get the effAddr. */
-    if (request->isMemAccessRequired()) {
-        if(isLoad) {
-            if (!inst->loadEffAddrValid()) {
-                inst->setLoadEffAddrs(request->getVaddr(), size);
-            }
-            // otherwise, assume that the instruction has set the addresses in advance
-        } else {
-            // store
-            if (!inst->effAddrValid())
-            {
-                inst->setEffAddrs(request->getVaddr(), size);
+    if (request->isTranslationComplete()) {
+        if (request->isMemAccessRequired()) {
+            if(isLoad) {
+                if (!inst->loadEffAddrValid()) {
+                    inst->setLoadEffAddrs(request->getVaddr(), size);
+                }
+                // otherwise, assume that the instruction has set the addresses in advance
+            } else {
+                // store
+                if (!inst->effAddrValid())
+                {
+                    inst->setEffAddrs(request->getVaddr(), size);
+                }
             }
-        }
 
-        if (cpu->checker) {
-            inst->reqToVerify = std::make_shared<Request>(*request->req());
-            inst->reqIdxToVerify = request->reqIdx;
-        }
-        Fault fault;
-        if (isLoad)
-            fault = read(request, inst->lqIdx);
-        else {
-            ++ inst->memWriteN;
-            fault = write(request, data, inst->sqIdx);
+            if (cpu->checker) {
+                inst->reqToVerify = std::make_shared<Request>(*request->req());
+                inst->reqIdxToVerify = request->reqIdx;
+            }
+            Fault fault;
+            if (isLoad)
+                fault = read(request, inst->lqIdx);
+            else {
+                ++ inst->memWriteN;
+                fault = write(request, data, inst->sqIdx);
+            }
+            // inst->getFault() may have the first-fault of a
+            // multi-access split request at this point.
+            // Overwrite that only if we got another type of fault
+            // (e.g. re-exec).
+            if (fault != NoFault)
+                inst->getFault() = fault;
+        } else if (isLoad) {
+            inst->setMemAccPredicate(false);
+            // Commit will have to clean up whatever happened.  Set this
+            // instruction as executed.
+            inst->setExecuted();
         }
-        // inst->getFault() may have the first-fault of a
-        // multi-access split request at this point.
-        // Overwrite that only if we got another type of fault
-        // (e.g. re-exec).
-        if (fault != NoFault)
-            inst->getFault() = fault;
-    } else if (isLoad) {
-        inst->setMemAccPredicate(false);
-        // Commit will have to clean up whatever happened.  Set this
-        // instruction as executed.
-        inst->setExecuted();
     }
 
     if (inst->traceData)

diff --git a/src/arch/riscvcapstone/o3/ncq_unit.cc b/src/arch/riscvcapstone/o3/ncq_unit.cc
@@ -227,6 +227,12 @@ NCQUnit::handleCacheResp(PacketPtr pkt) {
     assert(it != packetIssuers.end());
     PacketRecord& packet_record = it->second;
     NodeCommandPtr node_cmd = packet_record.cmd;
+    //check if it was a command issued by cpu and not an inst
+    if(!packet_record.inst && node_cmd == nullptr) {
+        packetIssuers.erase(it);
+        delete pkt;
+        return true;
+    }
     DPRINTF(NCQ, "Node cache response received for instruction %u, cmd beforeCommit = %u\n",
                     packet_record.inst->seqNum, node_cmd->beforeCommit());
 
@@ -301,6 +307,10 @@ NCQUnit::allocateInit() {
     cpu->nodeController.setRoot(0);
 
     if(pkt) {
+        packetIssuers[pkt->id] = PacketRecord {
+            .inst = nullptr,
+            .cmd = nullptr
+        };
         ncq->trySendPacket(pkt, threadId);
     }
 }

diff --git a/src/arch/riscvcapstone/tlb.cc b/src/arch/riscvcapstone/tlb.cc
@@ -339,10 +339,15 @@ TLB::translate(const RequestPtr &req, ThreadContext *tc,
 {
     delayed = false;
 
+    if(tc->cwrld() == 1) {
+        req->setPaddr(req->getVaddr());
+        return NoFault;
+    }
+
     if (FullSystem) {
         PrivilegeMode pmode = getMemPriv(tc, mode);
         SATP satp = tc->readMiscReg(MISCREG_SATP).intVal();
-        if (pmode == PrivilegeMode::PRV_M || satp.mode == AddrXlateMode::BARE || tc->cwrld() == 1)
+        if (pmode == PrivilegeMode::PRV_M || satp.mode == AddrXlateMode::BARE)
             req->setFlags(Request::PHYSICAL);
 
         Fault fault;