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#5 Re-issue rescheduled load
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@hakase56557
hakase56557 committed Aug 23, 2023
1 parent 29fdb2a commit c7600d3
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Showing 7 changed files with 29 additions and 20 deletions.
27 changes: 15 additions & 12 deletions src/arch/riscvcapstone/isa/decoder.isa
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Original file line number Diff line number Diff line change
Expand Up @@ -736,6 +736,7 @@ decode QUADRANT default Unknown::unknown() {
assert(Rs1_trv.getTag());

NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId();
if(dyn_inst->nodeQueryN == 0)
dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
}}, {{
Addr EA = Rs1_trv.getRegVal().capVal().cursor();
Expand All @@ -757,26 +758,26 @@ decode QUADRANT default Unknown::unknown() {
return std::make_shared<IllegalInstFault>(
"Rs1 doesn't have the necessary perms", machInst);

EA = EA & ~(sizeof(RegVal) - 1);
Fault fault = dyn_inst->initiateGetTag(EA);
//EA = EA & ~(sizeof(RegVal) - 1);
//Fault fault = dyn_inst->initiateGetTag(EA);
}}, {{
ConstTaggedRegVal temp_regval;
gem5::RiscvcapstoneISA::o3::Cap& cap = Mem_rv.capVal();
//gem5::RiscvcapstoneISA::o3::Cap& cap = Mem_ub.capVal();

getMemLE(pkt, cap, traceData);
getMemLE(pkt, Mem_ub, traceData);

Addr EA = Rs1_trv.getRegVal().capVal().cursor();
EA = EA & ~(sizeof(RegVal) - 1);
//Addr EA = Rs1_trv.getRegVal().capVal().cursor();
//EA = EA & ~(sizeof(RegVal) - 1);

temp_regval.getRegVal() = (uint8_t)Mem_rv;
temp_regval.getRegVal() = (uint8_t)Mem_ub;
temp_regval.setTag(false);

bool tag_res = dyn_inst->getTagQueryRes(0);
/*bool tag_res = dyn_inst->getTagQueryRes(0);
if(tag_res) {
dyn_inst->initiateSetTag(EA, false);
NodeID nodeId = Mem_rv.capVal().nodeId();
dyn_inst->initiateNodeCommand(new NodeRcUpdate(nodeId, -1));
}
}*/

Rd_trv = temp_regval;
//Rd_trv.setTag(false);
Expand All @@ -785,6 +786,7 @@ decode QUADRANT default Unknown::unknown() {
assert(Rs1_trv.getTag());

NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId();
if(dyn_inst->nodeQueryN == 0)
dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
}}, {{
Addr EA = Rs1_trv.getRegVal().capVal().cursor();
Expand All @@ -807,7 +809,8 @@ decode QUADRANT default Unknown::unknown() {
"Rs1 doesn't have the necessary perms", machInst);

EA = EA & ~(sizeof(RegVal) - 1);
Fault fault = dyn_inst->initiateGetTag(EA);
//if(dyn_inst->tagQueryN == 0)
// Fault fault = dyn_inst->initiateGetTag(EA);
}}, {{
ConstTaggedRegVal temp_regval;
gem5::RiscvcapstoneISA::o3::Cap& cap = Mem_rv.capVal();
Expand All @@ -820,12 +823,12 @@ decode QUADRANT default Unknown::unknown() {
temp_regval.getRegVal() = (uint64_t)Mem_rv;
temp_regval.setTag(false);

bool tag_res = dyn_inst->getTagQueryRes(0);
/*bool tag_res = dyn_inst->getTagQueryRes(0);
if(tag_res) {
dyn_inst->initiateSetTag(EA, false);
NodeID nodeId = Mem_rv.capVal().nodeId();
dyn_inst->initiateNodeCommand(new NodeRcUpdate(nodeId, -1));
}
}*/

Rd_trv = temp_regval;
//Rd_trv.setTag(false);
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2 changes: 2 additions & 0 deletions src/arch/riscvcapstone/isa/formats/tags.isa
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Original file line number Diff line number Diff line change
Expand Up @@ -110,6 +110,8 @@ def template TagAccessExecute {{

%(code)s;

dyn_inst->setLoadEffAddrs(EA, 1);

return NoFault;
}
}};
Expand Down
2 changes: 1 addition & 1 deletion src/arch/riscvcapstone/o3/commit.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -1228,7 +1228,7 @@ Commit::commitHead(const DynInstPtr &head_inst, unsigned inst_num)
//seriously, there has to be a better way to do this.
//how would split change RC? need to check the spec
std::string mnemonic = head_inst->staticInst->getName();
if(head_inst->staticInst->opClass() != No_OpClass && mnemonic != "capperm" &&
if(head_inst->fault != NoFault && head_inst->staticInst->opClass() != No_OpClass && mnemonic != "capperm" &&
mnemonic != "captype" && mnemonic != "capnode" &&
mnemonic != "capbound" && mnemonic != "stc" &&
mnemonic != "std" && mnemonic != "stb" &&
Expand Down
5 changes: 4 additions & 1 deletion src/arch/riscvcapstone/o3/iew.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -1295,7 +1295,10 @@ IEW::executeInsts()
if(fault == NoFault) {
DPRINTF(IEW, "Execute instruction %i -> %s\n", inst->seqNum, inst->staticInst->getName());
fault = inst->execute();
inst->setExecuteCalled();
//only one case will not mark executecalled -> when it's a rescheduled load
if(!inst->isLoad() || (inst->isLoad() && inst->loadEffAddrValid()) || inst->fault != NoFault)
inst->setExecuteCalled();

if(inst->isMemRef()) {
DPRINTF(IEW, "Memref fault = %d\n", fault == NoFault);
} else {
Expand Down
1 change: 0 additions & 1 deletion src/arch/riscvcapstone/o3/inst_queue.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -1097,7 +1097,6 @@ InstructionQueue::rescheduleMemInst(const DynInstPtr &resched_inst)
resched_inst->translationCompleted(false);

resched_inst->clearCanIssue();
//resched_inst->clearExecuteCalled();
memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
}

Expand Down
9 changes: 5 additions & 4 deletions src/arch/riscvcapstone/o3/lsq_unit.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -473,7 +473,7 @@ LSQUnit::checkSnoop(PacketPtr pkt)
LSQRequest *request = iter->request();

// Check that this snoop didn't just invalidate our lock flag
if (ld_inst->effAddrValid() &&
if (ld_inst->loadEffAddrValid() &&
request->isCacheBlockHit(invalidate_addr, cacheBlockMask)
&& ld_inst->memReqFlags & Request::LLSC) {
ld_inst->tcBase()->getIsaPtr()->handleLockedSnoopHit(ld_inst.get());
Expand All @@ -485,7 +485,7 @@ LSQUnit::checkSnoop(PacketPtr pkt)
ld_inst = iter->instruction();
assert(ld_inst);
request = iter->request();
if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered())
if (!ld_inst->loadEffAddrValid() || ld_inst->strictlyOrdered())
continue;

DPRINTF(LSQUnit, "-- inst [sn:%lli] to pktAddr:%#x\n",
Expand Down Expand Up @@ -1435,7 +1435,7 @@ LSQUnit::read(LSQRequest *request, ssize_t load_idx)
// rescheduled eventually
iewStage->rescheduleMemInst(load_inst);
load_inst->clearIssued();
load_inst->effAddrValid(false);
load_inst->loadEffAddrValid(false);
++stats.rescheduledLoads;
DPRINTF(LSQUnit, "Strictly ordered load [sn:%lli] PC %s\n",
load_inst->seqNum, load_inst->pcState());
Expand Down Expand Up @@ -1659,7 +1659,8 @@ LSQUnit::read(LSQRequest *request, ssize_t load_idx)
// rescheduled eventually
iewStage->rescheduleMemInst(load_inst);
load_inst->clearIssued();
load_inst->effAddrValid(false);
load_inst->loadEffAddrValid(false);
load_inst->memReadN--;
++stats.rescheduledLoads;

// Do not generate a writeback event as this instruction is not
Expand Down
3 changes: 2 additions & 1 deletion src/arch/riscvcapstone/o3/ncq_unit.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -92,7 +92,8 @@ NCQUnit::cleanupCommands(){
DPRINTF(NCQ, "Cleaning up commands\n");
while(!ncQueue.empty()) {
auto& front = ncQueue.front();
DPRINTF(NCQ, "cleanupCommands: inst %u, canWB %u, completed() %u, commands size() %u", front.inst->seqNum, front.canWB, front.completed(), front.commands.size());
DPRINTF(NCQ, "cleanupCommands: inst %u, canWB %u, completedCommands %u, commands size() %u\n",
front.inst->seqNum, front.canWB, front.completedCommands, front.commands.size());
if(front.canWB && front.completed()) {
DPRINTF(NCQ, "Removing NCQEntry for instruction %u\n", front.inst->seqNum);
front.inst->ncqIdx = -1;
Expand Down

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