[RV64_DYNAREC] Fixed SET_ELEMENT_WIDTH (#2260)

... also removed some unnecessary instructions in vector_loadmask
ptitSeb · Jan 14, 2025 · d91461f · d91461f
1 parent bcc497c
commit d91461f
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Showing 3 changed files with 16 additions and 19 deletions.
diff --git a/src/dynarec/rv64/dynarec_rv64_helper.c b/src/dynarec/rv64/dynarec_rv64_helper.c
@@ -3035,7 +3035,6 @@ void vector_loadmask(dynarec_rv64_t* dyn, int ninst, int vreg, uint64_t imm, int
                     int scratch = fpu_get_scratch(dyn);
                     vector_vsetvli(dyn, ninst, s1, VECTOR_SEW64, VECTOR_LMUL1, 1);
                     VMV_V_I(scratch, 1);
-                    VMV_S_X(vreg, xZR);
                     VSLIDE1UP_VX(vreg, scratch, xZR, VECTOR_UNMASKED);
                     vector_vsetvli(dyn, ninst, s1, sew, vlmul, multiple);
                     return;
@@ -3068,7 +3067,6 @@ void vector_loadmask(dynarec_rv64_t* dyn, int ninst, int vreg, uint64_t imm, int
                     vector_vsetvli(dyn, ninst, s1, VECTOR_SEW64, VECTOR_LMUL1, 1);
                     MOV64x(s1, 0x100000000ULL);
                     VMV_V_X(scratch, s1);
-                    VMV_S_X(vreg, xZR);
                     VSLIDE1UP_VX(vreg, scratch, xZR, VECTOR_UNMASKED);
                     vector_vsetvli(dyn, ninst, s1, sew, vlmul, multiple);
                     return;
@@ -3104,7 +3102,6 @@ void vector_loadmask(dynarec_rv64_t* dyn, int ninst, int vreg, uint64_t imm, int
                     vector_vsetvli(dyn, ninst, s1, VECTOR_SEW64, VECTOR_LMUL1, 1);
                     MOV64x(s1, 0x100000001ULL);
                     VMV_V_X(scratch, s1);
-                    VMV_S_X(vreg, xZR);
                     VSLIDE1UP_VX(vreg, scratch, xZR, VECTOR_UNMASKED);
                     vector_vsetvli(dyn, ninst, s1, sew, vlmul, multiple);
                     return;

diff --git a/src/dynarec/rv64/dynarec_rv64_helper.h b/src/dynarec/rv64/dynarec_rv64_helper.h
@@ -1147,16 +1147,16 @@
 #define MODREG ((nextop & 0xC0) == 0xC0)
 
 #ifndef SET_ELEMENT_WIDTH
-#define SET_ELEMENT_WIDTH(s1, sew, set)                                             \
-    do {                                                                            \
-        if (sew == VECTOR_SEWANY && dyn->vector_sew != VECTOR_SEWNA) {              \
-            dyn->vector_eew = dyn->vector_sew;                                      \
-        } else if (sew == dyn->vector_sew) {                                        \
-            dyn->vector_eew = dyn->vector_sew;                                      \
-        } else {                                                                    \
-            dyn->vector_eew = vector_vsetvli(dyn, ninst, s1, sew, VECTOR_LMUL1, 1); \
-        }                                                                           \
-        if (set) dyn->vector_sew = dyn->vector_eew;                                 \
+#define SET_ELEMENT_WIDTH(s1, sew, set)                                               \
+    do {                                                                              \
+        if ((sew) == VECTOR_SEWANY && dyn->vector_sew != VECTOR_SEWNA) {              \
+            dyn->vector_eew = dyn->vector_sew;                                        \
+        } else if ((sew) == dyn->vector_sew) {                                        \
+            dyn->vector_eew = dyn->vector_sew;                                        \
+        } else {                                                                      \
+            dyn->vector_eew = vector_vsetvli(dyn, ninst, s1, (sew), VECTOR_LMUL1, 1); \
+        }                                                                             \
+        if (set) dyn->vector_sew = dyn->vector_eew;                                   \
     } while (0)
 #endif
 

diff --git a/src/dynarec/rv64/dynarec_rv64_pass0.h b/src/dynarec/rv64/dynarec_rv64_pass0.h
@@ -86,10 +86,10 @@
         dynarec_log(LOG_NONE, "\n");                                                                                                                \
     }
 
-#define SET_ELEMENT_WIDTH(s1, sew, set)                  \
-    do {                                                 \
-        if (sew != VECTOR_SEWANY && set)                 \
-            dyn->vector_sew = sew;                       \
-        else if (dyn->vector_sew == VECTOR_SEWNA && set) \
-            dyn->vector_sew = VECTOR_SEW8;               \
+#define SET_ELEMENT_WIDTH(s1, sew, set)                    \
+    do {                                                   \
+        if ((sew) != VECTOR_SEWANY && (set))               \
+            dyn->vector_sew = (sew);                       \
+        else if (dyn->vector_sew == VECTOR_SEWNA && (set)) \
+            dyn->vector_sew = VECTOR_SEW8;                 \
     } while (0)