treewide: VC router + additional traffic generation & analysis (#47)

* creating files, mux, rr_arbiter * Adjustments to follow coding guidelines and hopefully pass linting checks * Not definite change as not changed in template: add vc_id, loohahead to hdr and add route_dir_e which allowes several output ports * floo_input_port, try to pass linting check * try to pass linting check * Fixed mistake in input port * Sa local stage in vc router * adhere to the holy laws of verible-lint * Added verible linter locally -> adhere to the holy rules of verible linter part 2 * sa global progress * fix mistake of having several data_v_i per port * work on transforming sa local outputs to sa global input * creating files, mux, rr_arbiter * Adjustments to follow coding guidelines and hopefully pass linting checks * floo_input_port, try to pass linting check * try to pass linting check * Sa local stage in vc router * adhere to the holy laws of verible-lint * Added verible linter locally -> adhere to the holy rules of verible linter part 2 * sa global progress * fix mistake of having several data_v_i per port * creating files, mux, rr_arbiter * Adjustments to follow coding guidelines and hopefully pass linting checks * floo_input_port, try to pass linting check * try to pass linting check * Sa local stage in vc router * adhere to the holy laws of verible-lint * Added verible linter locally -> adhere to the holy rules of verible linter part 2 * sa global progress * fix mistake of having several data_v_i per port * transform sa local output to sa global input in case of xyRouting * add select headerr mux to sa local, start lookahead routing * lookahead routing using floo_route_select * refactor sa local output to sa global input to use always_comb and int instead of genvar * adjust route_direction_e to have Eject at end, add dst_port_id to hdr, refactor floo_route_select to allow the index to be returned, to look at dst_port_id and to not return the one hot direction * typo in route_select * add credit_counter * reset route_direction_e values to ensure functionality remove leftovers of route_dir_e in lookahead * removed UsePortId from route_select as it would have required the corresponding hdr entry even if not needed. Added the (empty) connection to route_sel_id_o in floo_router * fix dimension mistake in credit counter * add vc selection * correct mistake in vc selection * add vc assignment * set vc_assignment_v to 0 if sa_global_v = 0 * remove unused param of vc assignment * fix typo in vc assignment * change read_enable_id to onehot in input port * change read_enable_id to onehot in input port pt 2 * change read_enable_id to onehot in input port pt 3 * map input to output and stage reg * add hdr FF, cleanup * start work on switch * Try to change the route_direction_e without failing tests * switch done * lookahead: allow source routing * add wormhole routing * cleanup floo_pkg and edit axi_pkg & narrow_wide_pkg in routing.py * adjust routing.py to follow pylint rules * fix issue of uninitialiyed port_id, adjust route_select to use port_id, remove usage of port_id from lookahead * add vc router to bender.yml and fix many mistakes * remove unused variables * start testbench for vc router, fix some errors * resolved many warnings, progress on tb * progress on vc router tb, got connectivity from North to South * cleanup rebase fckups and remove warning from test * remove unused variable which rebase readded * fix a verible lint error * vc router tb progress: test credits as well * add tb_floo_vc_router to gitlab ci * vc router tb progress: now tests all ports towards south, north, bugfix in credit_counter * vc router tb progress: test each vc to each vc done * test FVADA, dont display all info if Debug = 0 * refactor vc-router: dont need vc_id in sa_local, sa_global: just use onehot * test wormhole routing and fix wormhole routing * cleanup testbench * remove warning from vc_router * tb_floo_dma_mesh: change output fifo depth from 32 to more realistic 2 * add narrow_wide_chimney_cr * fix gitlab-ci, to also run tb_floo_dma_mesh_cr * add assertion that buffers are ready * Bugfixes in nw_chimney_cr and dma_mesh_cr * cleanup * fix wormhole routing * cleanup vc_assignment, add credit shortcut * typo in comment * update idma version * add file floo_input_fifo.sv * fix warning * fix tb_floo_vc_router to work with credit shortcut, add credit shortcut to chimney, add input_fifo to vc_router and chimney, bugfix in input_fifo * adjust chimney to use different vcs in case of several local ports * rename floo_.._cr to floo_vc_... * remove unused register * extend input_fifo to allow Depth of 1 (just a register) or 3 * add all traffic types supported by garnet (gem5): bit_complement, bit_reverse, bit_rotation, neighbor, shuffle, transpose, tornado * pylint fixes, add new traffic types to gitlab-ci * fix wormhole deadlock in sa_local * bugfix in transpose trafficgen * dma_experiments automation scripts * dma_experiments_analysis.py: pylint fixes * rr_arbiter fix potential deadlock * dma_experiments cleanup * fix issue with input fifo if used with depth 3 * allow tb_floo_vc_dma_mesh to be run with different ChannelFifoDepth * add traffic type single_dest_.. and add traffic_visualizations * add single_dest_.. traffic types to gitlab ci * try to remove possibly unnecessary waiting in testbenches * wait after tb ends in order to allow axi_bw_monitor to print * lint.yml install dependency pygame for traffic visualization * change dma_mesh testbenches to stop bw_monitor on per flow basis * move dependency pygame to pyproject.toml * adjust experiment analysis to calculate std of bw * add single dest traffic types * update adjustment: update if not sent but told to update * cleanup * vc_router update: add wormhole_vc which can be set to depth 3, add possibility to force wormhole flits to wormhole vc, add possibility to dissallow the deeper vc to overflow to other vcs * vc_router: add parameter to decide if rrArb should be updated if not sent but allowed to update * vc_router: try to update only sa_local if not sent (this push will fail tb_vc_dut) * try updateRRArb=1 but also AllowOverflowFromDeeperVC=1 * set UpdateRRArbIfNotSet to 0 in tb_floo_vc_router * add UpdateRRArbIfNotSent to vc_narrow_wide_router, set all values in tb_vc_dma to basic vc_router * set WormholeVCDepth to 3 and FixedWormholeVC to 1 * set AllowOverflowFromDeeperVC to 0 * turn off updateRRArbIfNotSent by default * support nonstandart number of VC: wrap around vc assignment * add Only1VC * add Jupyter file to analize dma_experiments results * add AllowVCOverflow parameter * make credit shortcut toggleable * adjust traffic visualization to use smoothstep * add parameter SingleStage to VC router: allow singleStage VC router * visualize_traffic: add still image visualization * include traffic_visualization pngs * rename boundry to boundary * rename boundry files to boundary * traffic visualizations cleanup * set router in tb_floo_vc_dma_mesh to 2 stage VCd2WHd3VCL1 * commit all plots and results in ipynb * fix rebase * hw: Small code clean-up * deps: Bump bender dependencies * test: Revert copying in of `tb_tasks.svh` file * hw: Clean-up * test: Remove comments * ci: Get rid of reviewdog * ci: Don't format sources explicitly * hw: Clean up `credit_counter` module * hw: `floo_input_fifo` minor improvements This module might benefit from a more general approach to the `Depth` parameter * floogen(pkg): Refer `rsvd` as `payload` in generic flit types * lint: TB sources * floogen(pkg): Define payload types * hw: `floo_input_port` Clean up * hw: Clean up `floo_rr_arbiter` * hw: Clean up `floo_mux` * hw: Clean up `floo_sa_local` * hw: Align VC nw chimney with new meta buffer interface * hw: Clean up `floo_sa_global` * hw: Clean up `floo_look_ahead_routing` * hw: Clean up `floo_route_select` * hw: Clean up `floo_vc_selection` * hw: Clean up `floo_vc_assigment` * hw: Rename signals in `floo_vc_router` * hw: Clean up `floo_vc_router` parameters * hw: Remove unused signals in `floo_vc_router` * hw: More clean up in `floo_vc_router` * hw: `floo_vc_router` whitespace changes * hw: linting * hw: `floo_vc_nw_router` Clean up * tb: Clean ups * tb: lint sources * hw: Clean up `floo_vc_narrow_wide_chimney` * doc: Update CHANGELOG * floogen(vc): Add own class for VC links * floogen(network): Add error message when compiling empty configurations * hw(pkg): Generate separate VC packages * test: Don't compile VC router by default * hw(pkg): Update `axi_pkg` sources as well * hw(pkg): Use port id by default * pkg: Also use `vc_axi_pkg` --------- Co-authored-by: sem24f5 Lukas Berner (bernerl) <[email protected]> Co-authored-by: sem24f5 Lukas Berner (bernerl) <[email protected]> Co-authored-by: Lukas Berner <[email protected]>
pulp-platform · Jul 23, 2024 · f5e9b00 · f5e9b00
1 parent 92d0f8c
commit f5e9b00
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diff --git a/.gitignore b/.gitignore
@@ -63,6 +63,7 @@ deps
 # Auto generated sources
 generated
 *.png
+!util/traffic_visualizations/*.png
 hw/test/jobs
 
 # QuestaSim
@@ -79,6 +80,9 @@ verible*
 # spyglass
 scripts/spyglass/*
 
+# experiment outputs
+util/output/*
+
 # Misc
 *.csv
 **/*.log

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -25,7 +25,7 @@ collect-bender-sources:
 compile-vsim:
   stage: build
   script:
-    - make compile-sim | tee compile.log 2>&1
+    - make compile-sim VC=true | tee compile.log 2>&1
     - '! grep "Error: " compile.log'
   needs:
     - collect-bender-sources
@@ -47,6 +47,7 @@ run-vsim:
     matrix:
       - VSIM_TB_DUT:
         - tb_floo_router
+        - tb_floo_vc_router
         - tb_floo_axi_chimney
         - tb_floo_narrow_wide_chimney
         - tb_floo_rob
@@ -61,11 +62,11 @@ run-vsim:
 run-traffic:
   stage: run
   variables:
-    VSIM_TB_DUT: tb_floo_dma_mesh
     JOB_NAME: mesh
   parallel:
     matrix:
-      - TRAFFIC_TYPE: [random, hbm, onehop]
+      - VSIM_TB_DUT: [tb_floo_dma_mesh, tb_floo_vc_dma_mesh]
+        TRAFFIC_TYPE: [random, hbm, onehop, bit_complement, bit_reverse, bit_rotation, neighbor, shuffle, transpose, tornado, single_dest_boundary, single_dest_center]
         TRAFFIC_RW: [read, write]
   needs:
     - collect-bender-sources

diff --git a/Bender.lock b/Bender.lock
@@ -7,8 +7,8 @@ packages:
     dependencies:
     - common_cells
   axi:
-    revision: fccffb5953ec8564218ba05e20adbedec845e014
-    version: 0.39.1
+    revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6
+    version: 0.39.3
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
@@ -24,9 +24,16 @@ packages:
     - axi
     - common_cells
     - common_verification
+  axi_stream:
+    revision: 54891ff40455ca94a37641b9da4604647878cc07
+    version: 0.1.1
+    source:
+      Git: https://github.com/pulp-platform/axi_stream.git
+    dependencies:
+    - common_cells
   common_cells:
-    revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f
-    version: 1.32.0
+    revision: 0d67563b6b592549542544f1abc0f43e5d4ee8b4
+    version: 1.35.0
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
@@ -39,24 +46,35 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   idma:
-    revision: ca1b28816a3706be0bf9ce01378246d5346384f0
-    version: 0.5.1
+    revision: 95f366e56f7e772c283fb3c8b343afc4a3978375
+    version: 0.6.2
     source:
       Git: https://github.com/pulp-platform/iDMA.git
     dependencies:
     - axi
+    - axi_stream
     - common_cells
     - common_verification
+    - obi
     - register_interface
+  obi:
+    revision: 1aa411df145c4ebdd61f8fed4d003c33f7b20636
+    version: 0.1.2
+    source:
+      Git: https://github.com/pulp-platform/obi.git
+    dependencies:
+    - common_cells
+    - common_verification
   register_interface:
-    revision: 146501d80052b61475cdc333d3aab4cd769fd5dc
-    version: 0.3.9
+    revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d
+    version: 0.4.4
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:
     - apb
     - axi
     - common_cells
+    - common_verification
   tech_cells_generic:
     revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
     version: 0.2.13

diff --git a/Bender.yml b/Bender.yml
@@ -9,11 +9,11 @@ package:
     - "Tim Fischer <[email protected]>"
 
 dependencies:
-  common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 }
-  common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2 }
-  axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 }
+  idma: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.6.2 }
+  common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.35.0 }
+  common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 }
+  axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.3 }
   axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.2 }
-  idma: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 }
 
 export_include_dirs:
   - hw/include
@@ -42,9 +42,30 @@ sources:
   - hw/floo_router.sv
   - hw/floo_narrow_wide_router.sv
 
+  - target: vc_router
+    files:
+      # Level 1
+      - hw/vc_router_util/floo_credit_counter.sv
+      - hw/vc_router_util/floo_input_fifo.sv
+      - hw/vc_router_util/floo_input_port.sv
+      - hw/vc_router_util/floo_look_ahead_routing.sv
+      - hw/vc_router_util/floo_mux.sv
+      - hw/vc_router_util/floo_rr_arbiter.sv
+      - hw/vc_router_util/floo_sa_global.sv
+      - hw/vc_router_util/floo_sa_local.sv
+      - hw/vc_router_util/floo_vc_assignment.sv
+      - hw/vc_router_util/floo_vc_router_switch.sv
+      - hw/vc_router_util/floo_vc_selection.sv
+      - hw/floo_vc_axi_pkg.sv
+      - hw/floo_vc_narrow_wide_pkg.sv
+      # Level 2
+      - hw/floo_vc_narrow_wide_chimney.sv
+      - hw/floo_vc_router.sv
+      - hw/floo_vc_narrow_wide_router.sv
+
   - target: test
     include_dirs:
-      - hw/test
+      - hw/test/include
     files:
       # Level 0
       - hw/test/floo_test_pkg.sv
@@ -64,3 +85,10 @@ sources:
       - hw/tb/tb_floo_dma_chimney.sv
       - hw/tb/tb_floo_dma_nw_chimney.sv
       - hw/tb/tb_floo_dma_mesh.sv
+
+  - target: all(test, vc_router)
+    include_dirs:
+      - hw/test/include
+    files:
+      - hw/tb/tb_floo_vc_router.sv
+      - hw/tb/tb_floo_vc_dma_mesh.sv
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -11,13 +11,19 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
 - Support for source-based routing algorithm in routers, chimnyes and `floogen`. The route is encoded in the header as a `route_t` field, and each router consumes a couple of bits to determine the output ports. In the chimney, a two-stage encoder was added to first determine the destination ID of the request, and then retrive the pre-computed route to that destination from a table. The `floogen` configuration was extended to support the new routing algorithm, and it will also generate the necessary tables for the chimneys.
 - Chimneys now support multiple AXI IDs for non-atomic transactions by specifying the `MaxUniqueids` parameter. This will mitigate ordering of transactions from initially different IDs or endpoints at the expense of some complexity in the `meta_buffer` which then uses `id_queue` to store the meta information required to return responses.
 - The conversion from req/rsp with different ID widths from/to NoC has been moved from the chimneys to the `floo_meta_buffer` module.
+- Added virtual channel router `floo_vc_router` and corresponding `floo_vc_narrow_wide_chimney`. Currently only supports XY-Routing and mesh topologies.
+- Preliminary support for multiple local ports in the routers.
+- Additional traffic pattern generation and visualization.
 
 ### Changed
 
 - `floo_route_comp` now supports source-based routing, and can output both destination ID and a route to the destination.
 - The chimneys have an additional port `route_table_i` to receive the pre-computed routing table that is generated by `floogen`.
 - System address map was renamed from `AddrMap` to `Sam`.
 - The destination field in the flit header have a new type `dst_t` which is either set to `route_t` for the new source-based routing algorithm, and `id_t` for all the other routing algorithms.
+- Bumped `idma` dependency to `0.6`
+- Renamed `rsvd` field in flits to `payload` to better reflect its purpose.
+- Reordered directions in `route_direction_e` to better support multiple local ports.
 
 ### Fixed
 

diff --git a/Makefile b/Makefile
@@ -31,6 +31,11 @@ VERIBLE_FMT	?= verible-verilog-format
 
 BENDER_FLAGS += -t rtl
 BENDER_FLAGS += -t test
+BENDER_FLAGS += -t snitch_cluster
+BENDER_FLAGS += -t idma_test
+ifdef VC
+	BENDER_FLAGS += -t vc_router
+endif
 
 VLOG_ARGS += -suppress vlog-2583
 VLOG_ARGS += -suppress vlog-13314

diff --git a/floo_noc.core b/floo_noc.core
@@ -2,8 +2,23 @@ CAPI=2:
 # Created by bender from the available manifest file.
 
 
-name: pulp-platform.org::floo_noc:0.3.0
+name: '::floo_noc:'
 filesets:
+  spyglass_or_synthesis:
+    file_type: systemVerilogSource
+    files:
+    - hw/test/floo_test_pkg.sv
+    - hw/synth/floo_synth_axi_chimney.sv
+    - hw/synth/floo_synth_narrow_wide_chimney.sv
+    - hw/synth/floo_synth_router.sv
+    - hw/synth/floo_synth_narrow_wide_router.sv
+    - hw/synth/floo_synth_endpoint.sv
+    depend:
+    - ::idma:0.6.0
+    - pulp-platform.org::common_cells:1.33.1
+    - pulp-platform.org::common_verification:0.2.3
+    - pulp-platform.org::axi:0.39.2
+    - ::axi_riscv_atomics:0.8.2
   files_rtl:
     file_type: systemVerilogSource
     files:
@@ -21,18 +36,34 @@ filesets:
     - hw/floo_rob.sv
     - hw/floo_rob_wrapper.sv
     - hw/floo_meta_buffer.sv
+    - hw/vc_router_util/floo_credit_counter.sv
+    - hw/vc_router_util/floo_input_fifo.sv
+    - hw/vc_router_util/floo_input_port.sv
+    - hw/vc_router_util/floo_look_ahead_routing.sv
+    - hw/vc_router_util/floo_mux.sv
+    - hw/vc_router_util/floo_rr_arbiter.sv
+    - hw/vc_router_util/floo_sa_global.sv
+    - hw/vc_router_util/floo_sa_local.sv
+    - hw/vc_router_util/floo_vc_assignment.sv
+    - hw/vc_router_util/floo_vc_router_switch.sv
+    - hw/vc_router_util/floo_vc_selection.sv
+    - hw/floo_narrow_wide_join.sv
     - hw/floo_axi_chimney.sv
     - hw/floo_narrow_wide_chimney.sv
+    - hw/floo_vc_narrow_wide_chimney.sv
     - hw/floo_router.sv
+    - hw/floo_vc_router.sv
     - hw/floo_narrow_wide_router.sv
+    - hw/floo_vc_narrow_wide_router.sv
     - hw/include/floo_noc/typedef.svh:
         is_include_file: true
         include_path: hw/include
     depend:
-    - pulp-platform.org::common_cells:1.32.0
+    - ::idma:0.6.0
+    - pulp-platform.org::common_cells:1.33.1
     - pulp-platform.org::common_verification:0.2.3
-    - pulp-platform.org::axi:0.39.1
-    - pulp-platform.org::idma:0.5.1
+    - pulp-platform.org::axi:0.39.2
+    - ::axi_riscv_atomics:0.8.2
   test:
     file_type: systemVerilogSource
     files:
@@ -47,35 +78,24 @@ filesets:
     - hw/tb/tb_floo_axi_chimney.sv
     - hw/tb/tb_floo_narrow_wide_chimney.sv
     - hw/tb/tb_floo_router.sv
+    - hw/tb/tb_floo_vc_router.sv
     - hw/tb/tb_floo_rob.sv
     - hw/tb/tb_floo_dma_chimney.sv
     - hw/tb/tb_floo_dma_nw_chimney.sv
     - hw/tb/tb_floo_dma_mesh.sv
-    - hw/test/include/axi_print_txns.svh:
+    - hw/tb/tb_floo_vc_dma_mesh.sv
+    - hw/test/include/tb_tasks.svh:
         is_include_file: true
         include_path: hw/test
-    - hw/test/include/tb_tasks.svh:
+    - hw/test/include/axi_print_txns.svh:
         is_include_file: true
         include_path: hw/test
     depend:
-    - pulp-platform.org::common_cells:1.32.0
-    - pulp-platform.org::common_verification:0.2.3
-    - pulp-platform.org::axi:0.39.1
-    - pulp-platform.org::idma:0.5.1
-  spyglass_or_synthesis:
-    file_type: systemVerilogSource
-    files:
-    - hw/test/floo_test_pkg.sv
-    - hw/synth/floo_synth_axi_chimney.sv
-    - hw/synth/floo_synth_narrow_wide_chimney.sv
-    - hw/synth/floo_synth_router.sv
-    - hw/synth/floo_synth_narrow_wide_router.sv
-    - hw/synth/floo_synth_endpoint.sv
-    depend:
-    - pulp-platform.org::common_cells:1.32.0
+    - ::idma:0.6.0
+    - pulp-platform.org::common_cells:1.33.1
     - pulp-platform.org::common_verification:0.2.3
-    - pulp-platform.org::axi:0.39.1
-    - pulp-platform.org::idma:0.5.1
+    - pulp-platform.org::axi:0.39.2
+    - ::axi_riscv_atomics:0.8.2
 targets:
   default:
     filesets:

diff --git a/floogen/examples/vc_axi_pkg.yml b/floogen/examples/vc_axi_pkg.yml
@@ -0,0 +1,37 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "narrow"
+description: "flit configuration for narrow-only AXI4 interfaces"
+
+routing:
+  route_algo: "XY"
+  use_id_table: false
+  addr_offset_bits: 16
+  num_x_bits: 3
+  num_y_bits: 3
+  port_id_bits: 2
+  num_vc_id_bits: 3
+
+protocols:
+  - name: "axi"
+    type: "AXI4"
+    direction: "manager"
+    data_width: 64
+    addr_width: 32
+    id_width: 3
+    user_width: 1
+  - name: "axi"
+    type: "AXI4"
+    direction: "subordinate"
+    data_width: 64
+    addr_width: 32
+    id_width: 3
+    user_width: 1
+
+endpoints: []
+
+routers: []
+
+connections: []