[cheshire] Parametrize FPGA flow #2390

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Job	Run time
tc-llvm	1m 19s
check-license	29s
check-trailing-whitespaces	5s
tc-gcc	52s
tc-isa-sim	32s
tc-verilator	11s
compile-ara (2_lanes)	3m 43s
compile-ara (4_lanes)	6m 29s
compile-ara (8_lanes)	12m 57s
compile-ara (16_lanes)	1h 52m 59s
check-clang-format	1m 16s
compile-apps (2_lanes)	1m 27s
compile-apps (4_lanes)	1s
compile-riscv-tests (2_lanes)	1m 23s
compile-riscv-tests (4_lanes)	1m 11s
compile-apps (8_lanes)	1s
compile-apps (16_lanes)	1s
compile-riscv-tests (8_lanes)	1m 11s
compile-riscv-tests (16_lanes)	1m 38s
riscv-tests-spike	1m 26s
riscv-tests-simv (2_lanes)	7m 32s
riscv-tests-simv (4_lanes)	18m 53s
benchmark	0s
riscv-tests-simv (8_lanes)	45m 46s
simulate	0s
riscv-tests-simv (16_lanes)	2h 26m 39s
roofline	0s
clean-up	5s
clean-up-compile-runs (2_lanes)	6s
clean-up-compile-runs (4_lanes)	6s
clean-up-compile-runs (8_lanes)	3s
clean-up-compile-runs (16_lanes)	6s
	6h 8m 27s