[CHANGELOG] Update Changelog #2038
mp-17ci.yml
on: push
tc-llvm
1h 35m
tc-isa-sim
2m 23s
tc-verilator
29s
tc-gcc
41m 53s
check-license
19s
check-trailing-whitespaces
10s
Matrix: compile-apps
check-clang-format
1m 12s
Matrix: compile-ara
Matrix: compile-riscv-tests
Matrix: simulate
Matrix: benchmark
Matrix: riscv-tests-simv
Annotations
6 errors
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check-clang-format
Process completed with exit code 1.
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benchmark (2_lanes)
Process completed with exit code 1.
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simulate (fconv3d, 16_lanes)
The run was canceled by @mp-17.
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simulate (fconv3d, 16_lanes)
The operation was canceled.
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riscv-tests-simv (16_lanes)
The run was canceled by @mp-17.
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riscv-tests-simv (16_lanes)
The operation was canceled.
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