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[hardware] 🐛 Consider LMUL when deciding if to reshuffle vd
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mp-17 committed Jun 18, 2024
1 parent 2c87cf4 commit f8263e6
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion hardware/src/ara_dispatcher.sv
Original file line number Diff line number Diff line change
Expand Up @@ -3195,7 +3195,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
// Optimization: reshuffle vd only if we are not overwriting the whole vector register!
reshuffle_req_d = {ara_req_d.use_vs1 && (ara_req_d.eew_vs1 != eew_q[ara_req_d.vs1]) && eew_valid_q[ara_req_d.vs1] && in_lane_op,
ara_req_d.use_vs2 && (ara_req_d.eew_vs2 != eew_q[ara_req_d.vs2]) && eew_valid_q[ara_req_d.vs2] && in_lane_op,
ara_req_d.use_vd && (ara_req_d.vtype.vsew != eew_q[ara_req_d.vd ]) && eew_valid_q[ara_req_d.vd ] && csr_vl_q != (VLENB >> ara_req_d.vtype.vsew)};
ara_req_d.use_vd && (ara_req_d.vtype.vsew != eew_q[ara_req_d.vd ]) && eew_valid_q[ara_req_d.vd ] && csr_vl_q != ((VLENB << ara_req_d.emul[1:0]) >> ara_req_d.vtype.vsew)};
// Mask out requests if they refer to the same register!
reshuffle_req_d &= {
(insn.varith_type.rs1 != insn.varith_type.rs2) && (insn.varith_type.rs1 != insn.varith_type.rd),
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