pulp-platform · yvantor · Jun 11, 2024 · Jun 12, 2024 · Jun 21, 2024 · Jun 22, 2024
@@ -0,0 +1,3 @@
+[submodule "sw/deps/cva6-sdk"]
+	path = sw/deps/cva6-sdk
+	url = https://github.com/pulp-platform/cva6-sdk.git
@@ -64,6 +64,10 @@ sources:
     files:
       - hw/configs/carfield_l2dual_safe_periph.sv
 
+  - target: carfield_l2dual_safe_spatz_periph
+    files:
+      - hw/configs/carfield_l2dual_safe_spatz_periph.sv
+
   - target: carfield_l2dual_spatz_periph
     files:
       - hw/configs/carfield_l2dual_spatz_periph.sv

@@ -47,7 +47,7 @@ include $(CAR_ROOT)/bender-safed.mk
 ######################
 
 CAR_NONFREE_REMOTE ?= [email protected]:astral/astral-nonfree.git
-CAR_NONFREE_COMMIT ?= e8e4354d084cf1cfe6eb9b3bae6af381ef9108b1 # branch: master
+CAR_NONFREE_COMMIT ?= a889b039cb9c77c879505eb64cbc8857a1349730 # branch: align-main
 
 ## @section Carfield platform nonfree components
 ## Clone the non-free verification IP for Carfield. Some components such as CI scripts and ASIC
@@ -247,19 +247,19 @@ regenerate_soc_regs: $(CAR_ROOT)/hw/regs/carfield_reg_pkg.sv $(CAR_ROOT)/hw/regs
 
 .PHONY: $(CAR_ROOT)/hw/regs/carfield_regs.hjson
 $(CAR_ROOT)/hw/regs/carfield_regs.hjson: hw/regs/carfield_regs.csv | venv
-	$(VENV)/python ./scripts/csv_to_json.py --input $< --output $@
+	$(VENV)/$(PYTHON) ./scripts/csv_to_json.py --input $< --output $@
 
 .PHONY: $(CAR_ROOT)/hw/regs/carfield_reg_pkg.sv hw/regs/carfield_reg_top.sv
 $(CAR_ROOT)/hw/regs/carfield_reg_pkg.sv $(CAR_ROOT)/hw/regs/carfield_reg_top.sv: $(CAR_ROOT)/hw/regs/carfield_regs.hjson | venv
-	$(VENV)/python utils/reggen/regtool.py -r $< --outdir $(dir $@)
+	$(VENV)/$(PYTHON) utils/reggen/regtool.py -r $< --outdir $(dir $@)
 
 .PHONY: $(CAR_SW_DIR)/include/regs/soc_ctrl.h
 $(CAR_SW_DIR)/include/regs/soc_ctrl.h: $(CAR_ROOT)/hw/regs/carfield_regs.hjson | venv
-	$(VENV)/python utils/reggen/regtool.py -D $<  > $@
+	$(VENV)/$(PYTHON) utils/reggen/regtool.py -D $<  > $@
 
 .PHONY: $(CAR_SW_DIR)/hw/regs/pcr.md
 $(CAR_HW_DIR)/regs/pcr.md: $(CAR_ROOT)/hw/regs/carfield_regs.hjson | venv
-	$(VENV)/python utils/reggen/regtool.py -d $<  > $@
+	$(VENV)/$(PYTHON) utils/reggen/regtool.py -d $<  > $@
 
 ## Update host domain PLIC and CLINT interrupt controllers configuration. The default configuration
 ## in cheshire allows for one interruptible hart. When the number of external interruptible harts is

@@ -60,9 +60,9 @@ See below some typical building time for reference:
 
 | Config                                 | Board  | Duration   |
 |----------------------------------------|--------|------------|
-| carfield_l2dual_pulp_periph            | vcu128 | __ISSUE__  |
-| carfield_l2dual_safe_periph            | vcu128 | 6h01min    |
-| carfield_l2dual_spatz_periph           | vcu128 | 3h31min    |
+| carfield_l2dual_pulp_periph            | vcu128 | ~5h        |
+| carfield_l2dual_safe_periph            | vcu128 | ~5h        |
+| carfield_l2dual_spatz_periph           | vcu128 | ~5h        |
 | carfield_l2dual_secure_periph          | vcu128 | __ISSUE__  |
 
 You can find which sources are used by looking at `Bender.yml` (target `all(xilinx, fpga,
@@ -104,14 +104,15 @@ See the argument list below:
 | GEN_EXT_JTAG    | vcu128    | `0` Connect the JTAG debugger to the board's JTAG (see [vcu128](#xilinx-vcu128)) <br>`1` Connect the JTAG debugger to an external JTAG chain |
 | CARFIELD_CONFIG | all       | Select the Carfield configuration to implement. See below for supported configs.                                                      |
 | VIVADO_MODE     | all       | `batch` Compile in Vivado shell<br>`gui` Compile in Vivado gui                                                                        |
+| XILINX_BOOT_ETH | all       | `0` Boot via SPI flash only (see [booting Linux](#booting_linux)) <br>`1` Boot via SPI flash and Ethernet                             |
 
 See below some typical building time for reference:
 
 | Config                                 | Board  | Duration   |
 |----------------------------------------|--------|------------|
-| carfield_l2dual_pulp_periph            | vcu128 | __ISSUE__  |
-| carfield_l2dual_safe_periph            | vcu128 | 3h49min    |
-| carfield_l2dual_spatz_periph           | vcu128 | 5h40min    |
+| carfield_l2dual_pulp_periph            | vcu128 | ~5h        |
+| carfield_l2dual_safe_periph            | vcu128 | ~5h        |
+| carfield_l2dual_spatz_periph           | vcu128 | ~5h        |
 | carfield_l2dual_secure_periph          | vcu128 | __ISSUE__  |
 
 You can find which sources are used by looking at `Bender.yml` (target `all(xilinx, fpga,
@@ -124,6 +125,10 @@ Note that the `make` command above will first package a Carfield ip before compi
 
 ## Board specificities
 
+### All
+> #### Ethernet
+> As the MAC address of each FPGA is unique (but reconfigurable), if you wish to use the Ethernet
+> IP (`bd` flavor) you will need to add the MAC address of your board in `sw/boot/mac_address.dtsi`.
 ### Xilinx VCU128
 > #### Bootmodes and VIOs
 >
@@ -198,10 +203,6 @@ Tbd
 
 Tbd
 
-### JTAG Preloading
-
-Tbd
-
 ## Booting Linux
 
 To boot Linux, we must load the *OpenSBI* firmware, which takes over M mode and launches the U-boot
@@ -211,8 +212,8 @@ Clone the `carfield` branch of CVA6 SDK at the root of this repository and build
 (OpenSBI + U-boot) and Linux images (*this will take about 30 minutes*):
 
 ```bash
-git clone https://github.com/pulp-platform/cva6-sdk.git --branch carfield
-make -C cva6-sdk images
+git submodule update --init --recursive sw/deps/cva6-sdk
+make -C sw/deps/cva6-sdk images
 ```
 
 In principle, we can boot Linux through JTAG by loading all images into memory, launching OpenSBI,
@@ -227,16 +228,14 @@ To create a full Linux disk image from the ZSL, device tree, firmware, and Linux
 
 ```bash
 # Place the cva6-sdk where they are expected:
-ln -s cva6-sdk/install64 sw/boot/install64
-# Optional: Pre-uild explicitely the image
+ln -s sw/deps/cva6-sdk/install64 sw/boot/install64
+# Optional: Pre-build explicitely the image
 make CAR_ROOT=. sw/boot/linux_carfield_bd_vcu128.gpt.bin
 ```
 
-You can now recompile the board, it should start booting automatically!
-
-### Xilinx VCU128
+### Via SPI flash
 >
-> This board does not offer a SD card reader. We need to load the image in the
+> Boards like VCU128 does not offer a SD card reader. We need to load the image in the
 integrated flash:
 >
 > ```
@@ -248,6 +247,21 @@ integrated flash:
 >
 > This script will erase your bitstream, once the flash has been written (c.a.
 10min) you will need to re-program the bitstream on the board.
+> You can attach the UART port of the FPGA to minicom and see the boot process! 
+### Via Ethernet
+>
+> As flashing and reading the kernel from SPI can take a few minutes, a faster way is to
+> [ask U-Boot to fetch the image from the network](https://www.emcraft.com/som/using-dhcp).
+> This feature can be enabled in the Carfield `bd` flavor. You will need to add the MAC
+> address of your FPGA in `sw/boot/mac_address.dtsi` and the path to your Linux image (on a FTP server)
+> in `sw/boot/remote_boot.dtsi`.
+> You will still need to flash u-boot but it will be now faster:
+> ```
+> make chs-xil-flash VIVADO_MODE=batch XILINX_BOARD=vcu128 XILINX_FLAVOR=bd XILINX_BOOT_ETH=1
+> ```
+### Via Ethernet
+
+Tbd
 
 ## Add your own board
 

@@ -1281,7 +1281,7 @@ else begin : gen_no_safety_island
   assign safed_secd_mbox_intr = '0;
 
   assign safed_dbg_reqs = '0;
-  assign jtag_safety_island_tdo_o = '0;
+  assign jtag_safety_island_tdo_o = jtag_safety_island_tdi_i;
 end
 
 // PULP integer cluster
@@ -1795,7 +1795,7 @@ end else begin : gen_no_secure_subsystem
   assign car_regs_hw2reg.security_island_isolate_status.d = '0;
   assign car_regs_hw2reg.security_island_isolate_status.de = '0;
 
-  assign jtag_ot_tdo_o = '0;
+  assign jtag_ot_tdo_o = jtag_ot_tdi_i;
 end
 
 // Mailbox unit

@@ -0,0 +1,84 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Yvan Tortorella <[email protected]>
+
+package carfield_configuration;
+
+import cheshire_pkg::*;
+/*********************
+ * AXI Configuration *
+ ********************/
+//L2, port 0
+localparam bit     L2Port0Enable = 1;
+localparam doub_bt L2Port0Base = 'h78000000;
+localparam doub_bt L2Port0Size = 'h00200000;
+// L2, port 1
+localparam bit     L2Port1Enable = 1;
+localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size;
+localparam doub_bt L2Port1Size = L2Port0Size;
+// Safety Island
+localparam bit     SafetyIslandEnable = 1;
+localparam doub_bt SafetyIslandBase = 'h60000000;
+localparam doub_bt SafetyIslandSize = 'h00800000;
+// Ethernet
+localparam bit     EthernetEnable = 0;
+localparam doub_bt EthernetBase = 'h20000000;
+localparam doub_bt EthernetSize = 'h00001000;
+// Peripherals
+localparam bit     PeriphEnable = 1;
+localparam doub_bt PeriphBase = 'h20001000;
+localparam doub_bt PeriphSize = 'h00009000;
+// Spatz cluster
+localparam bit     SpatzClusterEnable = 1;
+localparam doub_bt SpatzClusterBase = 'h51000000;
+localparam doub_bt SpatzClusterSize = 'h00800000;
+// PULP cluster
+localparam bit     PulpClusterEnable = 0;
+localparam doub_bt PulpClusterBase = 'h50000000;
+localparam doub_bt PulpClusterSize = 'h00800000;
+// Security Island
+localparam bit     SecurityIslandEnable = 0;
+localparam doub_bt SecurityIslandBase = 'h0;
+localparam doub_bt SecurityIslandSize = 'h0;
+// Mailbox
+localparam bit     MailboxEnable = 1;
+localparam doub_bt MailboxBase = 'h40000000;
+localparam doub_bt MailboxSize = 'h00001000;
+// Can
+localparam bit CanEnable = 0;
+localparam doub_bt CanBase = 'h20001000;
+localparam doub_bt CanSize = 'h00001000;
+// System Timer
+localparam doub_bt SystemTimerBase = 'h20004000;
+localparam doub_bt SystemTimerSize = 'h00001000;
+// System Advanced Timer
+localparam doub_bt SystemAdvancedTimerBase = 'h20005000;
+localparam doub_bt SystemAdvancedTimerSize = 'h00001000;
+// System Watchdog
+localparam doub_bt SystemWatchdogBase = 'h20007000;
+localparam doub_bt SystemWatchdogSize = 'h00001000;
+// Hyperbus Config
+localparam doub_bt HyperBusBase = 'h20009000;
+localparam doub_bt HyperBusSize = 'h00001000;
+/************************
+ * RegBus Configuration *
+ ***********************/
+// Platform control registers
+localparam doub_bt PcrsBase = 'h20010000;
+localparam doub_bt PcrsSize = 'h00001000;
+// PLL
+localparam bit     PllCfgEnable = 1;
+localparam doub_bt PllCfgBase = 'h20020000;
+localparam doub_bt PllCfgSize = 'h00001000;
+// Padframe
+localparam bit     PadframeCfgEnable = 1;
+localparam doub_bt PadframeCfgBase = 'h200A0000;
+localparam doub_bt PadframeCfgSize = 'h00001000;
+// L2 ECC
+localparam bit     L2EccCfgEnable = 1;
+localparam doub_bt L2EccCfgBase = 'h200B0000;
+localparam doub_bt L2EccCfgSize = 'h00001000;
+
+endpackage
@@ -29,7 +29,7 @@ localparam doub_bt EthernetSize = 'h00001000;
 // Peripherals
 localparam bit     PeriphEnable = 1;
 localparam doub_bt PeriphBase = 'h20001000;
-localparam doub_bt PeriphSize = 'h00009000;
+localparam doub_bt PeriphSize = 'h01000000;
 // Spatz cluster
 localparam bit     SpatzClusterEnable = 0;
 localparam doub_bt SpatzClusterBase = 'h51000000;
@@ -63,25 +63,25 @@ localparam doub_bt SystemAdvancedTimerSize = 'h00001000;
 localparam doub_bt SystemWatchdogBase = 'h20007000;
 localparam doub_bt SystemWatchdogSize = 'h00001000;
 // Hyperbus Config
-localparam doub_bt HyperBusBase = 'h20009000;
+localparam doub_bt HyperBusBase = 'h20008000;
 localparam doub_bt HyperBusSize = 'h00001000;
 /************************
  * RegBus Configuration *
  ***********************/
-// Platform control registers
-localparam doub_bt PcrsBase = 'h20010000;
-localparam doub_bt PcrsSize = 'h00001000;
-// PLL
-localparam bit     PllCfgEnable = 1;
-localparam doub_bt PllCfgBase = 'h20020000;
-localparam doub_bt PllCfgSize = 'h00001000;
 // Padframe
 localparam bit     PadframeCfgEnable = 1;
-localparam doub_bt PadframeCfgBase = 'h200A0000;
+localparam doub_bt PadframeCfgBase = 'h21000000;
 localparam doub_bt PadframeCfgSize = 'h00001000;
 // L2 ECC
 localparam bit     L2EccCfgEnable = 1;
-localparam doub_bt L2EccCfgBase = 'h200B0000;
+localparam doub_bt L2EccCfgBase = 'h21001000;
 localparam doub_bt L2EccCfgSize = 'h00001000;
+// Platform control registers
+localparam doub_bt PcrsBase = 'h21002000;
+localparam doub_bt PcrsSize = 'h00001000;
+// PLL
+localparam bit     PllCfgEnable = 1;
+localparam doub_bt PllCfgBase = 'h21003000;
+localparam doub_bt PllCfgSize = 'h00001000;
 
 endpackage
@@ -12,3 +12,4 @@ yapf
 mkdocs
 mkdocs-material
 mkdocs-glightbox
+pandas
-Original file line number
+Diff line change
@@ Expand Up / @@ -12,3 +12,4 @@ yapf @@
     mkdocs
     mkdocs-material
     mkdocs-glightbox
+    pandas