src: Remove missing pin warnings

src/axi_mcast_demux.sv

@@ -1125,8 +1125,8 @@ module axi_mcast_demux_intf #(
   input  rule_t   default_mst_port_i,
   AXI_BUS.Slave   slv,                   // slave port
   AXI_BUS.Master  mst [NO_MST_PORTS-1:0], // master ports
-  output logic    [NoMstPorts-1:0] mst_is_mcast_o,
-  output logic    [NoMstPorts-1:0] mst_aw_commit_o
+  output logic    [NO_MST_PORTS-1:0] mst_is_mcast_o,
+  output logic    [NO_MST_PORTS-1:0] mst_aw_commit_o
 );
 
   typedef logic [AXI_ID_WIDTH-1:0]       id_t;

src/axi_to_mem_interleaved.sv

@@ -282,6 +282,8 @@ module axi_to_mem_interleaved_intf #(
   input  logic                          clk_i,
   /// Asynchronous reset, active low
   input  logic                          rst_ni,
+  /// Testmode enable
+  input  logic                          test_i,
   /// Status output, busy flag of `axi_to_mem`
   output logic                          busy_o,
   /// AXI4+ATOP slave port
@@ -337,6 +339,7 @@ module axi_to_mem_interleaved_intf #(
   ) i_axi_to_mem_interleaved (
     .clk_i,
     .rst_ni,
+    .test_i,
     .busy_o,
     .axi_req_i  ( mem_axi_req  ),
     .axi_resp_o ( mem_axi_resp ),

src/axi_to_mem_split.sv

@@ -196,6 +196,8 @@ module axi_to_mem_split_intf #(
   input  logic                               clk_i,
   /// Asynchronous reset, active low.
   input  logic                               rst_ni,
+  /// Testmode enable
+  input  logic                               test_i,
   /// See `axi_to_mem_split`, port `busy_o`.
   output logic                               busy_o,
   /// AXI4+ATOP slave interface port.
@@ -244,6 +246,7 @@ module axi_to_mem_split_intf #(
   ) i_axi_to_mem_split (
     .clk_i,
     .rst_ni,
+    .test_i,
     .busy_o,
     .axi_req_i (axi_req),
     .axi_resp_o (axi_resp),