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Create per-channel user signals #314

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Create per-channel user signals #314

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29fa1fa
First batch of user modifications
thommythomaso May 9, 2023
9a80c70
Second batch of user modifications
thommythomaso May 10, 2023
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140 changes: 79 additions & 61 deletions include/axi/typedef.svh
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@
// - Andreas Kurth <[email protected]>
// - Florian Zaruba <[email protected]>
// - Wolfgang Roenninger <[email protected]>
// - Thomas Benz <[email protected]>

// Macros to define AXI and AXI-Lite Channel and Request/Response Structs

Expand All @@ -23,62 +24,62 @@
// AXI4+ATOP Channel and Request/Response Structs
//
// Usage Example:
// `AXI_TYPEDEF_AW_CHAN_T(axi_aw_t, axi_addr_t, axi_id_t, axi_user_t)
// `AXI_TYPEDEF_W_CHAN_T(axi_w_t, axi_data_t, axi_strb_t, axi_user_t)
// `AXI_TYPEDEF_B_CHAN_T(axi_b_t, axi_id_t, axi_user_t)
// `AXI_TYPEDEF_AR_CHAN_T(axi_ar_t, axi_addr_t, axi_id_t, axi_user_t)
// `AXI_TYPEDEF_R_CHAN_T(axi_r_t, axi_data_t, axi_id_t, axi_user_t)
// `AXI_TYPEDEF_AW_CHAN_T(axi_aw_t, axi_addr_t, axi_id_t, axi_aw_user_t)
// `AXI_TYPEDEF_W_CHAN_T(axi_w_t, axi_data_t, axi_strb_t, axi_w_user_t)
// `AXI_TYPEDEF_B_CHAN_T(axi_b_t, axi_id_t, axi_b_user_t)
// `AXI_TYPEDEF_AR_CHAN_T(axi_ar_t, axi_addr_t, axi_id_t, axi_ar_user_t)
// `AXI_TYPEDEF_R_CHAN_T(axi_r_t, axi_data_t, axi_id_t, axi_r_user_t)
// `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_t, axi_w_t, axi_ar_t)
// `AXI_TYPEDEF_RESP_T(axi_resp_t, axi_b_t, axi_r_t)
`define AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) \
typedef struct packed { \
id_t id; \
addr_t addr; \
axi_pkg::len_t len; \
axi_pkg::size_t size; \
axi_pkg::burst_t burst; \
logic lock; \
axi_pkg::cache_t cache; \
axi_pkg::prot_t prot; \
axi_pkg::qos_t qos; \
axi_pkg::region_t region; \
axi_pkg::atop_t atop; \
user_t user; \
`define AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t) \
typedef struct packed { \
id_t id; \
addr_t addr; \
axi_pkg::len_t len; \
axi_pkg::size_t size; \
axi_pkg::burst_t burst; \
logic lock; \
axi_pkg::cache_t cache; \
axi_pkg::prot_t prot; \
axi_pkg::qos_t qos; \
axi_pkg::region_t region; \
axi_pkg::atop_t atop; \
aw_user_t user; \
} aw_chan_t;
`define AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) \
typedef struct packed { \
data_t data; \
strb_t strb; \
logic last; \
user_t user; \
`define AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t) \
typedef struct packed { \
data_t data; \
strb_t strb; \
logic last; \
w_user_t user; \
} w_chan_t;
`define AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) \
typedef struct packed { \
id_t id; \
axi_pkg::resp_t resp; \
user_t user; \
`define AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t) \
typedef struct packed { \
id_t id; \
axi_pkg::resp_t resp; \
b_user_t user; \
} b_chan_t;
`define AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) \
typedef struct packed { \
id_t id; \
addr_t addr; \
axi_pkg::len_t len; \
axi_pkg::size_t size; \
axi_pkg::burst_t burst; \
logic lock; \
axi_pkg::cache_t cache; \
axi_pkg::prot_t prot; \
axi_pkg::qos_t qos; \
axi_pkg::region_t region; \
user_t user; \
`define AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t) \
typedef struct packed { \
id_t id; \
addr_t addr; \
axi_pkg::len_t len; \
axi_pkg::size_t size; \
axi_pkg::burst_t burst; \
logic lock; \
axi_pkg::cache_t cache; \
axi_pkg::prot_t prot; \
axi_pkg::qos_t qos; \
axi_pkg::region_t region; \
ar_user_t user; \
} ar_chan_t;
`define AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) \
typedef struct packed { \
id_t id; \
data_t data; \
axi_pkg::resp_t resp; \
logic last; \
user_t user; \
`define AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t) \
typedef struct packed { \
id_t id; \
data_t data; \
axi_pkg::resp_t resp; \
logic last; \
r_user_t user; \
} r_chan_t;
`define AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) \
typedef struct packed { \
Expand All @@ -105,27 +106,44 @@


////////////////////////////////////////////////////////////////////////////////////////////////////
// All AXI4+ATOP Channels and Request/Response Structs in One Macro - Custom Type Name Version
// All AXI4+ATOP Channels and Request/Response Structs in One Macro - Custom Type Name and
// Per-channel Custom User Signal Version
//
// This can be used whenever the user is not interested in "precise" control of the naming of the
// individual channels.
//
// Usage Example:
// `AXI_TYPEDEF_ALL_CT(axi, axi_req_t, axi_rsp_t, addr_t, id_t, data_t, strb_t, user_t)
// `AXI_TYPEDEF_ALL_CT_PU(axi, axi_req_t, axi_rsp_t, addr_t, id_t, data_t, strb_t, aw_user_t, w_user_t, b_user_t, ar_user_t, r_user_t)
//
// This defines `axi_req_t` and `axi_rsp_t` request/response structs as well as `axi_aw_chan_t`,
// `axi_w_chan_t`, `axi_b_chan_t`, `axi_ar_chan_t`, and `axi_r_chan_t` channel structs.
`define AXI_TYPEDEF_ALL_CT(__name, __req, __rsp, __addr_t, __id_t, __data_t, __strb_t, __user_t) \
`AXI_TYPEDEF_AW_CHAN_T(__name``_aw_chan_t, __addr_t, __id_t, __user_t) \
`AXI_TYPEDEF_W_CHAN_T(__name``_w_chan_t, __data_t, __strb_t, __user_t) \
`AXI_TYPEDEF_B_CHAN_T(__name``_b_chan_t, __id_t, __user_t) \
`AXI_TYPEDEF_AR_CHAN_T(__name``_ar_chan_t, __addr_t, __id_t, __user_t) \
`AXI_TYPEDEF_R_CHAN_T(__name``_r_chan_t, __data_t, __id_t, __user_t) \
`AXI_TYPEDEF_REQ_T(__req, __name``_aw_chan_t, __name``_w_chan_t, __name``_ar_chan_t) \
`define AXI_TYPEDEF_ALL_CT_PU(__name, __req, __rsp, __addr_t, __id_t, __data_t, __strb_t, __aw_user_t, __w_user_t, __b_user_t, __ar_user_t, __r_user_t) \
`AXI_TYPEDEF_AW_CHAN_T(__name``_aw_chan_t, __addr_t, __id_t, __aw_user_t) \
`AXI_TYPEDEF_W_CHAN_T(__name``_w_chan_t, __data_t, __strb_t, __w_user_t) \
`AXI_TYPEDEF_B_CHAN_T(__name``_b_chan_t, __id_t, __b_user_t) \
`AXI_TYPEDEF_AR_CHAN_T(__name``_ar_chan_t, __addr_t, __id_t, __ar_user_t) \
`AXI_TYPEDEF_R_CHAN_T(__name``_r_chan_t, __data_t, __id_t, __r_user_t) \
`AXI_TYPEDEF_REQ_T(__req, __name``_aw_chan_t, __name``_w_chan_t, __name``_ar_chan_t) \
`AXI_TYPEDEF_RESP_T(__rsp, __name``_b_chan_t, __name``_r_chan_t)
////////////////////////////////////////////////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////////////////////////////////////////////
// All AXI4+ATOP Channels and Request/Response Structs in One Macro - Custom Type Name Version
//
// This can be used whenever the user is not interested in "precise" control of the naming of the
// individual channels.
//
// Usage Example:
// `AXI_TYPEDEF_ALL_CT_PU(axi, axi_req_t, axi_rsp_t, addr_t, id_t, data_t, strb_t, user_t)
//
// This defines `axi_req_t` and `axi_rsp_t` request/response structs as well as `axi_aw_chan_t`,
// `axi_w_chan_t`, `axi_b_chan_t`, `axi_ar_chan_t`, and `axi_r_chan_t` channel structs.
`define AXI_TYPEDEF_ALL_CT(__name, __req, __rsp, __addr_t, __id_t, __data_t, __strb_t, __user_t) \
`AXI_TYPEDEF_ALL_CT_PU(__name, __req, __rsp, __addr_t, __id_t, __data_t, __strb_t, __user_t, __user_t, __user_t, __user_t, __user_t)
////////////////////////////////////////////////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////////////////////////////////////////////
// All AXI4+ATOP Channels and Request/Response Structs in One Macro
//
Expand All @@ -137,8 +155,8 @@
//
// This defines `axi_req_t` and `axi_resp_t` request/response structs as well as `axi_aw_chan_t`,
// `axi_w_chan_t`, `axi_b_chan_t`, `axi_ar_chan_t`, and `axi_r_chan_t` channel structs.
`define AXI_TYPEDEF_ALL(__name, __addr_t, __id_t, __data_t, __strb_t, __user_t) \
`AXI_TYPEDEF_ALL_CT(__name, __name``_req_t, __name``_resp_t, __addr_t, __id_t, __data_t, __strb_t, __user_t)
`define AXI_TYPEDEF_ALL(__name, __addr_t, __id_t, __data_t, __strb_t, __user_t) \
`AXI_TYPEDEF_ALL_CT(__name, __name``_req_t, __name``_resp_t, __addr_t, __id_t, __data_t, __strb_t, __user_t, __user_t, __user_t, __user_t, __user_t)
////////////////////////////////////////////////////////////////////////////////////////////////////


Expand Down
47 changes: 31 additions & 16 deletions src/axi_atop_filter.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -374,15 +374,25 @@ endmodule
/// Interface variant of [`axi_atop_filter`](module.axi_atop_filter).
module axi_atop_filter_intf #(
/// AXI ID width
parameter int unsigned AXI_ID_WIDTH = 0,
parameter int unsigned AXI_ID_WIDTH = 32'd0,
/// AXI address width
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
/// AXI data width
parameter int unsigned AXI_DATA_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 32'd0,
/// AXI user signal width
parameter int unsigned AXI_USER_WIDTH = 0,
parameter int unsigned AXI_USER_WIDTH = 32'd0,
/// Maximum number of in-flight AXI write transactions
parameter int unsigned AXI_MAX_WRITE_TXNS = 0
parameter int unsigned AXI_MAX_WRITE_TXNS = 32'd0,
/// AXI AW user signal width
parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH,
/// AXI W user signal width
parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH,
/// AXI B user signal width
parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH,
/// AXI AR user signal width
parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH,
/// AXI R user signal width
parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH
) (
/// Rising-edge clock of both ports
input logic clk_i,
Expand All @@ -394,17 +404,22 @@ module axi_atop_filter_intf #(
AXI_BUS.Master mst
);

typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;

`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t;
typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t;
typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t;
typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t;
typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t;

`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t)
`AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)

Expand Down
48 changes: 31 additions & 17 deletions src/axi_cdc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -124,12 +124,22 @@ endmodule

// interface wrapper
module axi_cdc_intf #(
parameter int unsigned AXI_ID_WIDTH = 0,
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
parameter int unsigned AXI_USER_WIDTH = 0,
parameter int unsigned AXI_ID_WIDTH = 32'd0,
parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
parameter int unsigned AXI_DATA_WIDTH = 32'd0,
parameter int unsigned AXI_USER_WIDTH = 32'd0,
/// AXI AW user signal width
parameter int unsigned AXI_AW_USER_WIDTH = AXI_USER_WIDTH,
/// AXI W user signal width
parameter int unsigned AXI_W_USER_WIDTH = AXI_USER_WIDTH,
/// AXI B user signal width
parameter int unsigned AXI_B_USER_WIDTH = AXI_USER_WIDTH,
/// AXI AR user signal width
parameter int unsigned AXI_AR_USER_WIDTH = AXI_USER_WIDTH,
/// AXI R user signal width
parameter int unsigned AXI_R_USER_WIDTH = AXI_USER_WIDTH,
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LOG_DEPTH = 1
parameter int unsigned LOG_DEPTH = 32'd1
) (
// slave side - clocked by `src_clk_i`
input logic src_clk_i,
Expand All @@ -141,18 +151,22 @@ module axi_cdc_intf #(
AXI_BUS.Master dst
);

typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_AW_USER_WIDTH-1:0] aw_user_t;
typedef logic [AXI_W_USER_WIDTH-1:0] w_user_t;
typedef logic [AXI_B_USER_WIDTH-1:0] b_user_t;
typedef logic [AXI_AR_USER_WIDTH-1:0] ar_user_t;
typedef logic [AXI_R_USER_WIDTH-1:0] r_user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, aw_user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, w_user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, b_user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, ar_user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, r_user_t)
`AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)

req_t src_req, dst_req;
resp_t src_resp, dst_resp;
Expand Down
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