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Adds a simple Regbus to AXI4 adapter.
Valid Regbus requests are locked in until a response (B/R) is received. The data width must match on both ends. The address is truncated or zero-extended as required by the provided type parameters. AXI4 AX requests are sent with ID 0 and user signals 0. The cache signals are parameterizable for convenience.
The module was tested in Cheshire by using it to adapt the SpinalHDL USB control interface from AXI4 to Regbus. All tests pass and USB works as expected on FPGA.