Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

axi_sim_mem: Configure response data #338

Merged
merged 1 commit into from
May 8, 2024
Merged

axi_sim_mem: Configure response data #338

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 2 additions & 0 deletions CHANGELOG.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.


## Unreleased
### Added
- `axi_sim_mem`: Allow response data for uninitialized region to have configurable defined value.

## 0.39.2 - 2024-03-13

Expand Down
15 changes: 14 additions & 1 deletion src/axi_sim_mem.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,8 @@ module axi_sim_mem #(
parameter type axi_rsp_t = logic,
/// Warn on accesses to uninitialized bytes
parameter bit WarnUninitialized = 1'b0,
/// Default value for uninitialized memory (undefined, zeros, ones, random)
parameter UninitializedData = "undefined",
/// Clear error on access
parameter bit ClearErrOnAccess = 1'b0,
/// Application delay (measured after rising clock edge)
Expand Down Expand Up @@ -241,7 +243,16 @@ module axi_sim_mem #(
$warning("Access to non-initialized byte at address 0x%016x by ID 0x%x.", byte_addr,
r_beat.id);
end
r_data[i_byte*8+:8] = 'x;
case (UninitializedData)
"random":
r_data[i_byte*8+:8] = $urandom;
"ones":
r_data[i_byte*8+:8] = '1;
"zeros":
r_data[i_byte*8+:8] = '0;
default:
r_data[i_byte*8+:8] = 'x;
endcase
end else begin
r_data[i_byte*8+:8] = mem[byte_addr];
end
Expand Down Expand Up @@ -342,6 +353,7 @@ module axi_sim_mem_intf #(
parameter int unsigned AXI_ID_WIDTH = 32'd0,
parameter int unsigned AXI_USER_WIDTH = 32'd0,
parameter bit WARN_UNINITIALIZED = 1'b0,
parameter UNINITIALIZED_DATA = "undefined",
parameter bit ClearErrOnAccess = 1'b0,
parameter time APPL_DELAY = 0ps,
parameter time ACQ_DELAY = 0ps
Expand Down Expand Up @@ -386,6 +398,7 @@ module axi_sim_mem_intf #(
.axi_req_t (axi_req_t),
.axi_rsp_t (axi_resp_t),
.WarnUninitialized (WARN_UNINITIALIZED),
.UninitializedData (UNINITIALIZED_DATA),
.ClearErrOnAccess (ClearErrOnAccess),
.ApplDelay (APPL_DELAY),
.AcqDelay (ACQ_DELAY)
Expand Down
Loading