[feature] Implement MemPool DMA and ITA as peripheral

Cargo.toml

@@ -25,6 +25,7 @@ llvm-sys = "120"
 log = { version = "0.4", features = ["release_max_level_info"] }
 pest = "2.1.3"
 pest_derive = "2.1.0"
+ndarray = "0.13"
 pretty_env_logger = "0.4"
 rev_slice = "0.1.5"
 serde = { version = "1.0.123", features = ["derive"] }

config/mempool.yaml

@@ -11,28 +11,39 @@ address:
   nr_cores: 0x40000010
   uart: 0xC0000000
   # Not supported in MemPool
-  barrier_reg: 0x50000000
+  barrier_reg:
+    start: 0x50000000
+    offset: 0x100000
   cluster_base_hartid: 0x50000001
   cluster_num: 0x50000002
   cluster_id: 0x50000003
   cl_clint: 0x40000060
   clint: 0xFFFF0000
 memory:
-  - tcdm:
-      start: 0x0
-      end: 0x100000
-      latency: 5
-    dram:
-      start: 0x80000000
-      end: 0x80010000
-      latency: 10
-    # Not used in MemPool
-    ext_tcdm: []
-    periphs:
-      callbacks: []
-      end: 0x100000
-      latency: 5
-      start: 0x100000
+  tcdm:
+    start: 0x0
+    size: 0x100000
+    offset: 0x100000
+    latency: 5
+  dram:
+    start: 0x80000000
+    size: 0x01000000
+    offset: 0x0
+    latency: 10
+  periphs:
+    start: 0x40000000
+    size: 0x20000
+    offset: 0x0
+    latency: 5
+    callbacks:
+      - name: zero-memory
+        size: 0x40
+      - name: mempool-ita
+        size: 32
+      - name: zero-memory
+        size: 0xFFA0
+      - name: mempool-dma
+        size: 28
 inst_latency:
   mul: 3
   mulh: 3

src/engine.rs

@@ -713,7 +713,7 @@ impl<'a, 'b> Cpu<'a, 'b> {
         }
     }
 
-    fn binary_load(&self, addr: u32, size: u8) -> u32 {
+    pub fn binary_load(&self, addr: u32, size: u8) -> u32 {
         match addr {
             x if x == self.engine.config.address.tcdm_start => {
                 self.engine.config.memory.tcdm.start
@@ -801,7 +801,7 @@ impl<'a, 'b> Cpu<'a, 'b> {
                 let periph_addr = addr
                     - (self.engine.config.memory.periphs.start
                         + self.engine.config.memory.periphs.offset * id as u32);
-                self.engine.peripherals.load(id, periph_addr, size)
+                self.engine.peripherals.load(&self, id, periph_addr, size)
             }
             // Bootrom
             x if x >= self.engine.config.bootrom.start
@@ -854,7 +854,7 @@ impl<'a, 'b> Cpu<'a, 'b> {
         }
     }
 
-    fn binary_store(&self, addr: u32, value: u32, mask: u32, size: u8) {
+    pub fn binary_store(&self, addr: u32, value: u32, mask: u32, size: u8) {
         match addr {
             x if x == self.engine.config.address.tcdm_start => (), // tcdm_start
             x if x == self.engine.config.address.tcdm_end => (),   // tcdm_end
@@ -950,7 +950,7 @@ impl<'a, 'b> Cpu<'a, 'b> {
                         + self.engine.config.memory.periphs.offset * id as u32);
                 self.engine
                     .peripherals
-                    .store(id, periph_addr, value, mask, size)
+                    .store(&self, id, periph_addr, value, mask, size)
             }
             // Bootrom
             x if x >= self.engine.config.bootrom.start
@@ -1055,6 +1055,29 @@ impl<'a, 'b> Cpu<'a, 'b> {
         prev as u32
     }
 
+    pub fn binary_memcpy(&self, mut dest: u32, mut src: u32, n: u32) {
+        // n in bytes
+        trace!("MEMCPY From {:08x} to {:08x} num: {:08x}", src, dest, n);
+        if dest % 4 == 0 && src % 4 == 0 && n % 4 == 0 {
+            warn!("MEMCPY aligned");
+            // Aligned transfer
+            for _ in 0..n / 4 {
+                let tmp = self.binary_load(src, 2);
+                self.binary_store(dest, tmp, u32::MAX, 2);
+                src += 4;
+                dest += 4;
+            }
+        } else {
+            warn!("MEMCPY unaligned");
+            for _ in 0..n {
+                let tmp = self.binary_load(src, 0);
+                self.binary_store(dest, tmp, (u8::MAX as u32) << (8 * (dest % 4)), 0);
+                src += 1;
+                dest += 1;
+            }
+        }
+    }
+
     fn binary_csr_read(&self, csr: riscv::Csr, notrace: u32) -> u32 {
         if notrace == 0 {
             trace!("Read CSR {:?}", csr);