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fpga: Adding pads in vanilla
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@CyrilKoe
CyrilKoe committed Aug 29, 2024
1 parent a3b96bd commit 44fb3e4
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4 changes: 4 additions & 0 deletions target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc
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Expand Up @@ -5,7 +5,11 @@
# Cyril Koenig <[email protected]>

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {design_1_i/carfield_xilinx_ip_0/inst/i_carfield_xilinx/gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O]

############
# Hyperbus #
############

#set_property PACKAGE_PIN A16 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71
#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71
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42 changes: 42 additions & 0 deletions target/xilinx/flavor_vanilla/constraints/vcu128_hyperbus.xdc
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Expand Up @@ -5,6 +5,48 @@
# Cyril Koenig <[email protected]>

set_property CLOCK_DEDICATED_ROUTE FALSE [get_ports pad_hyper_rwds[0]]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O]


set period_hyperbus 100

create_clock -period [expr $period_hyperbus] -name hyper_rwds_clk [get_ports pad_hyper_rwds[0]]

create_generated_clock -name hyper_clk_phy -source [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/CLK] -divide_by 2 [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/clock_generator.ddr_clk/r_clk0_o_reg/Q]
create_generated_clock -name hyper_clk_phy_90 -source [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/CLK] -edges {2 4 6} [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/clock_generator.ddr_clk/r_clk90_o_reg/Q]

set clk_rwds_delayed_pin [get_pins -of_objects [get_cells i_carfield/i_hyperbus_wrap/i_hyperbus/i_phy/i_phy/i_trx/i_delay_rx_rwds_90/i_delay] -filter {DIRECTION =~ OUT}]
set clk_rwds_delayed_inv_pin [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/i_phy/i_phy/i_trx/i_rx_rwds_cdc_fifo/CLK]

set clk_rx_shift [expr $period_hyperbus/10]
set rwds_input_delay [expr $period_hyperbus/4]
create_generated_clock -name hyper_clk_rwds_delayed0 -edges {1 2 3} -edge_shift "$clk_rx_shift $clk_rx_shift $clk_rx_shift" \
-source [get_ports pad_hyper_rwds[0]] $clk_rwds_delayed_pin
set_clock_latency [expr ${rwds_input_delay}] hyper_clk_rwds_delayed0

create_generated_clock -name hyper_clk_rwds_sample0 -invert -divide_by 1 -source $clk_rwds_delayed_pin $clk_rwds_delayed_inv_pin
set_clock_latency [expr ${rwds_input_delay}] hyper_clk_rwds_sample0

set_false_path -from [get_ports pad_hyper_rwds[0]] -to [get_ports pad_hyper_rwds[0]]
# these are for clock domain crossing
set_false_path -from [get_clocks hyper_rwds_clk] -to [get_clocks hyper_clk_phy]
set_false_path -from [get_clocks hyper_clk_phy] -to [get_clocks hyper_rwds_clk]
set_false_path -from [get_clocks hyper_clk_phy_90] -to [get_clocks hyper_clk_phy]
set_false_path -from [get_clocks hyper_clk_phy_90] -to [get_clocks hyper_rwds_clk]

# Todo correct build correct input / output constraints

set hyper_output_ports [get_ports pad_hyper_dq*]
set_output_delay [expr $period_hyperbus/2 ] -clock hyper_clk_phy [get_ports $hyper_output_ports] -max
set_output_delay [expr $period_hyperbus/-2] -clock hyper_clk_phy [get_ports $hyper_output_ports] -min -add_delay
set_output_delay [expr $period_hyperbus/2 ] -clock hyper_clk_phy [get_ports $hyper_output_ports] -max -clock_fall -add_delay
set_output_delay [expr $period_hyperbus/-2] -clock hyper_clk_phy [get_ports $hyper_output_ports] -min -clock_fall -add_delay

set hyper_input_ports [get_ports -regexp pad_hyper_dq.*]
set_input_delay -max [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports]
set_input_delay -min [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports] -add_delay
set_input_delay -max [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports] -add_delay -clock_fall
set_input_delay -min [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports] -add_delay -clock_fall

#set_property PACKAGE_PIN A16 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71
#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71
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112 changes: 100 additions & 12 deletions target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -121,7 +121,7 @@ module carfield_top_xilinx
`elsif USE_RESETN
logic cpu_reset;
assign cpu_reset = ~cpu_resetn;
`endif
`endif // USE_RESET
logic sys_rst;

wire clk_100, clk_50, clk_20;
Expand All @@ -140,17 +140,17 @@ module carfield_top_xilinx
assign testmode_i = '0;
assign boot_mode_i = 2'b00;
assign boot_mode_safety_i = 2'b00;
`endif
`endif // USE_SWITCHES

// Give VDD and GND to JTAG
`ifdef USE_JTAG_VDDGND
assign jtag_vdd_o = '1;
assign jtag_gnd_o = '0;
`endif
`endif // USE_JTAG_VDDGND
`ifndef USE_JTAG_TRSTN
logic jtag_trst_ni;
assign jtag_trst_ni = '1;
`endif
`endif // USE_JTAG_TRSTN
`ifndef USE_JTAG
logic jtag_tck_i;
logic jtag_tms_i;
Expand All @@ -159,7 +159,7 @@ module carfield_top_xilinx
assign jtag_tck_i = '0;
assign jtag_tms_i = '0;
assign jtag_tdi_i = '0;
`endif
`endif // USE_JTAG

//////////////////
// Clock Wizard //
Expand Down Expand Up @@ -227,11 +227,11 @@ module carfield_top_xilinx
assign sys_rst = cpu_reset | vio_reset;
assign boot_mode = boot_mode_i | vio_boot_mode;
assign boot_mode_safety = boot_mode_safety_i | vio_boot_mode_safety;
`else
`else // USE_VIO
assign sys_rst = cpu_reset;
assign boot_mode = boot_mode_i;
assign boot_mode_safety = boot_mode_safety_i;
`endif
`endif // USE_VIO

//////////////////
// I2C Adaption //
Expand Down Expand Up @@ -275,7 +275,7 @@ module carfield_top_xilinx
.I ( i2c_sda_soc_out ),
.T ( ~i2c_sda_en )
);
`endif
`endif // USE_I2C


//////////////////
Expand Down Expand Up @@ -403,7 +403,7 @@ module carfield_top_xilinx
.pwm_setting_i ( fan_sw ),
.fan_pwm_o ( fan_pwm )
);
`endif
`endif // USE_FAN

//////////////////
// Carfield Cfg //
Expand All @@ -417,6 +417,7 @@ module carfield_top_xilinx
///////////////////

`ifdef GEN_NO_HYPERBUS // bender-xilinx.mk

localparam axi_in_t AxiIn = gen_axi_in(Cfg);
localparam int unsigned LlcIdWidth = Cfg.AxiMstIdWidth+$clog2(AxiIn.num_in)+Cfg.LlcNotBypass;
localparam int unsigned LlcArWidth = (2**LogDepth)*axi_pkg::ar_width(Cfg.AddrWidth,LlcIdWidth,Cfg.AxiUserWidth);
Expand Down Expand Up @@ -475,6 +476,82 @@ module carfield_top_xilinx
.dst_req_o ( llc_req ),
.dst_resp_i ( llc_rsp )
);
`endif // GEN_NO_HYPERBUS

///////////////////
// Hyperram PADS //
///////////////////

`ifndef GEN_NO_HYPERBUS

logic [`HypNumPhys-1:0][`HypNumChips-1:0] hyper_cs_no;
logic [`HypNumPhys-1:0] hyper_ck_o;
logic [`HypNumPhys-1:0] hyper_ck_no;
logic [`HypNumPhys-1:0] hyper_rwds_o;
logic [`HypNumPhys-1:0] hyper_rwds_i;
logic [`HypNumPhys-1:0] hyper_rwds_oe_o;
logic [`HypNumPhys-1:0][7:0] hyper_dq_i;
logic [`HypNumPhys-1:0][7:0] hyper_dq_o;
logic [`HypNumPhys-1:0] hyper_dq_oe_o;
logic [`HypNumPhys-1:0] hyper_reset_no;

for (genvar i = 0 ; i < `HypNumPhys; i++) begin : gen_hyper_phy

for (genvar j = 0; j < `HypNumChips; j++) begin : gen_hyper_cs
pad_functional_pd padinst_hyper_csno (
.OEN ( 1'b0 ),
.I ( hyper_cs_no[i][j] ),
.O ( ),
.PEN ( ),
.PAD ( pad_hyper_csn[i][j] )
);
end // gen_hyper_cs

pad_functional_pd padinst_hyper_ck (
.OEN ( 1'b0 ),
.I ( hyper_ck_o[i] ),
.O ( ),
.PEN ( ),
.PAD ( pad_hyper_ck[i] )
);
pad_functional_pd padinst_hyper_ckno (
.OEN ( 1'b0 ),
.I ( hyper_ck_no[i] ),
.O ( ),
.PEN ( ),
.PAD ( pad_hyper_ckn[i] )
);
pad_functional_pd padinst_hyper_rwds0 (
.OEN ( ~hyper_rwds_oe_o[i] ),
.I ( hyper_rwds_o[i] ),
.O ( hyper_rwds_i[i] ),
.PEN ( ),
.PAD ( pad_hyper_rwds[i] )
);

for (genvar j = 0; j < 8; j++) begin : gen_hyper_dq
pad_functional_pd padinst_hyper_dqio0 (
.OEN ( ~hyper_dq_oe_o[i] ),
.I ( hyper_dq_o[i][j] ),
.O ( hyper_dq_i[i][j] ),
.PEN ( ),
.PAD ( pad_hyper_dq[i][j] )
);
end // gen_hyper_dq

end // gen_hyper_phy

`ila(ila_hyper_cs_n , hyper_cs_no )
`ila(ila_hyper_ck , hyper_ck_o )
`ila(ila_hyper_ck_n , hyper_ck_no )
`ila(ila_hyper_rwds_o , hyper_rwds_o )
`ila(ila_hyper_rwds_i , hyper_rwds_i )
`ila(ila_hyper_rwds_oe_o , hyper_rwds_oe_o )
`ila(ila_hyper_dq_i , hyper_dq_i )
`ila(ila_hyper_dq_o , hyper_dq_o )
`ila(ila_hyper_dq_oe , hyper_dq_oe_o )
`ila(ila_hyper_reset_n , hyper_reset_no )

`endif // GEN_NO_HYPERBUS

//////////////////
Expand All @@ -494,7 +571,7 @@ module carfield_top_xilinx
.LlcBWidth ( LlcBWidth ),
.LlcRWidth ( LlcRWidth ),
.LlcWWidth ( LlcWWidth ),
`endif
`endif // GEN_NO_HYPERBUS
.HypNumPhys (`HypNumPhys),
.HypNumChips (`HypNumChips)
) i_carfield (
Expand Down Expand Up @@ -576,7 +653,18 @@ module carfield_top_xilinx
.llc_w_data,
.llc_w_wptr,
.llc_w_rptr,
`endif
`else // GEN_NO_HYPERBUS
.hyper_cs_no,
.hyper_ck_o,
.hyper_ck_no,
.hyper_rwds_o,
.hyper_rwds_i,
.hyper_rwds_oe_o,
.hyper_dq_i,
.hyper_dq_o,
.hyper_dq_oe_o,
.hyper_reset_no,
`endif // GEN_NO_HYPERBUS
// Serial link interface
.slink_rcv_clk_i (),
.slink_rcv_clk_o (),
Expand Down Expand Up @@ -610,6 +698,6 @@ module carfield_top_xilinx
// Phy
.*
);
`endif
`endif // USE_DDR

endmodule

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