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target/sim: Add VCS simulation flow #163

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merged 8 commits into from
Jan 8, 2025

make: Use Bender flags variable for VCS compile script

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Merged

target/sim: Add VCS simulation flow #163

make: Use Bender flags variable for VCS compile script
2ada27a
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GitHub Actions / verible-verilog-lint succeeded Jan 8, 2025 in 0s

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