Add l1 events

pulp-platform · Jun 28, 2024 · 10b58ff · 10b58ff
1 parent aaf6f6b
commit 10b58ff
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Showing 7 changed files with 49 additions and 7 deletions.
diff --git a/Changelog.md b/Changelog.md
@@ -6,6 +6,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 
 ## Unreleased
+### Added
+- Add statistics signals output for shared L1.
 
 ## 0.1.1 - 28.06.2024
 ### Added

diff --git a/src/snitch_icache.sv b/src/snitch_icache.sv
@@ -63,6 +63,7 @@ module snitch_icache import snitch_icache_pkg::*; #(
 
   input  logic                                    enable_prefetching_i,
   output icache_l0_events_t [NR_FETCH_PORTS-1:0]  icache_l0_events_o,
+  output icache_l1_events_t                       icache_l1_events_o,
 
   input  logic [NR_FETCH_PORTS-1:0]               flush_valid_i,
   output logic [NR_FETCH_PORTS-1:0]               flush_ready_o,
@@ -536,6 +537,7 @@ module snitch_icache import snitch_icache_pkg::*; #(
 
       .flush_valid_i   ( flush_valid_lookup        ),
       .flush_ready_o   ( flush_ready_lookup        ),
+      .icache_events_o ( icache_l1_events_o        ),
 
       .in_addr_i       ( prefetch_lookup_req.addr  ),
       .in_id_i         ( prefetch_lookup_req.id    ),
@@ -574,6 +576,7 @@ module snitch_icache import snitch_icache_pkg::*; #(
 
       .flush_valid_i   ( flush_valid_lookup        ),
       .flush_ready_o   ( flush_ready_lookup        ),
+      .icache_events_o ( icache_l1_events_o        ),
 
       .in_addr_i       ( prefetch_lookup_req.addr  ),
       .in_id_i         ( prefetch_lookup_req.id    ),

diff --git a/src/snitch_icache_lookup_parallel.sv b/src/snitch_icache_lookup_parallel.sv
@@ -5,8 +5,8 @@
 // Fabian Schuiki <[email protected]>
 
 /// An actual cache lookup.
-module snitch_icache_lookup_parallel #(
-  parameter snitch_icache_pkg::config_t CFG = '0,
+module snitch_icache_lookup_parallel import snitch_icache_pkg::*; #(
+  parameter config_t CFG = '0,
   /// Configuration input types for SRAMs used in implementation.
   parameter type sram_cfg_data_t  = logic,
   parameter type sram_cfg_tag_t   = logic
@@ -16,6 +16,7 @@ module snitch_icache_lookup_parallel #(
 
   input  logic flush_valid_i,
   output logic flush_ready_o,
+  output icache_l1_events_t           icache_events_o,
 
   input  logic [CFG.FETCH_AW-1:0]    in_addr_i,
   input  logic [CFG.ID_WIDTH-1:0]    in_id_i,
@@ -250,6 +251,17 @@ module snitch_icache_lookup_parallel #(
   assign out_error_o = data_q.error;
   assign out_valid_o = buffer_valid;
 
+  // ------------------
+  // Performance Events
+  // ------------------
+  always_comb begin
+    icache_events_o = '0;
+    icache_events_o.l1_miss = valid_q & ~data_d.hit;
+    icache_events_o.l1_hit = valid_q & data_d.hit;
+    icache_events_o.l1_stall = in_valid_i & ~in_ready_o;
+    icache_events_o.l1_handler_stall = out_valid_o & ~out_ready_i;
+  end
+
   // Assertions
   `include "common_cells/assertions.svh"
   `ASSERT(i_rsp_buffer_ready, (valid_q |-> buffer_ready), clk_i, !rst_ni)

diff --git a/src/snitch_icache_lookup_serial.sv b/src/snitch_icache_lookup_serial.sv
@@ -7,8 +7,8 @@
 `include "common_cells/registers.svh"
 
 /// An actual cache lookup.
-module snitch_icache_lookup_serial #(
-  parameter snitch_icache_pkg::config_t CFG = '0,
+module snitch_icache_lookup_serial import snitch_icache_pkg::*; #(
+  parameter config_t CFG = '0,
   /// Configuration input types for SRAMs used in implementation.
   parameter type sram_cfg_data_t  = logic,
   parameter type sram_cfg_tag_t   = logic
@@ -18,6 +18,7 @@ module snitch_icache_lookup_serial #(
 
   input  logic                       flush_valid_i,
   output logic                       flush_ready_o,
+  output icache_l1_events_t          icache_events_o,
 
   input  logic [CFG.FETCH_AW-1:0]    in_addr_i,
   input  logic [CFG.ID_WIDTH-1:0]    in_id_i,
@@ -334,4 +335,15 @@ module snitch_icache_lookup_serial #(
   assign out_valid_o = data_valid;
   assign data_ready  = out_ready_i;
 
+  // ------------------
+  // Performance Events
+  // ------------------
+  always_comb begin
+    icache_events_o = '0;
+    icache_events_o.l1_miss = req_handshake & ~tag_rsp_s.hit;
+    icache_events_o.l1_hit = req_handshake & tag_rsp_s.hit;
+    icache_events_o.l1_stall = in_valid_i & ~in_ready_o;
+    icache_events_o.l1_handler_stall = out_valid_o & ~out_ready_i;
+  end
+
 endmodule
diff --git a/src/snitch_icache_pkg.sv b/src/snitch_icache_pkg.sv
@@ -14,6 +14,13 @@ package snitch_icache_pkg;
     logic l0_stall;
   } icache_l0_events_t;
 
+  typedef struct packed {
+    logic l1_miss;
+    logic l1_hit;
+    logic l1_stall;
+    logic l1_handler_stall;
+  } icache_l1_events_t;
+
   typedef struct packed {
     // Parameters passed to the root module.
     int unsigned NR_FETCH_PORTS;

diff --git a/src/snitch_read_only_cache.sv b/src/snitch_read_only_cache.sv
@@ -8,7 +8,7 @@
 /// Serve read memory requests from a read-only cache.
 /// The cacheable region can be runtime configured. All writes and read
 /// requests outside the configured regions will be forwarded.
-module snitch_read_only_cache #(
+module snitch_read_only_cache import snitch_icache_pkg::*; #(
   /// Cache Line Width
   parameter int unsigned LineWidth    = -1,
   /// The number of cache lines per set. Power of two; >= 2.
@@ -39,6 +39,7 @@ module snitch_read_only_cache #(
   input  logic                                     enable_i,
   input  logic                                     flush_valid_i,
   output logic                                     flush_ready_o,
+  output icache_l1_events_t                        icache_events_o,
   input  logic [NrAddrRules-1:0][AxiAddrWidth-1:0] start_addr_i,
   input  logic [NrAddrRules-1:0][AxiAddrWidth-1:0] end_addr_i,
   input  slv_req_t                                 axi_slv_req_i,
@@ -191,7 +192,7 @@ module snitch_read_only_cache #(
   // Cache Logic
   // --------------------------------------------------
   localparam int unsigned PendingCount = MaxTrans;
-  localparam snitch_icache_pkg::config_t CFG = '{
+  localparam config_t CFG = '{
     LINE_WIDTH:         LineWidth,
     LINE_COUNT:         LineCount,
     SET_COUNT:          SetCount,
@@ -293,6 +294,7 @@ module snitch_read_only_cache #(
 
       .flush_valid_i ( flush_valid_i ),
       .flush_ready_o ( flush_ready_o ),
+      .icache_events_o,
 
       .in_addr_i     ( in_addr       ),
       .in_id_i       ( in_id         ),
@@ -330,6 +332,7 @@ module snitch_read_only_cache #(
 
       .flush_valid_i ( flush_valid_i ),
       .flush_ready_o ( flush_ready_o ),
+      .icache_events_o,
 
       .in_addr_i     ( in_addr       ),
       .in_id_i       ( in_id         ),

diff --git a/test/snitch_read_only_cache_tb.sv b/test/snitch_read_only_cache_tb.sv
@@ -379,12 +379,15 @@ module snitch_read_only_cache_tb #(
     .enable_i      ( 1'b1                ),
     .flush_valid_i ( 1'b0                ),
     .flush_ready_o ( /*unused*/          ),
+    .icache_events_o (  ),
     .start_addr_i  ( {CachedRegionStart} ),
     .end_addr_i    ( {CachedRegionEnd}   ),
     .axi_slv_req_i ( axi_mst_req         ),
     .axi_slv_rsp_o ( axi_mst_resp        ),
     .axi_mst_req_o ( axi_slv_req         ),
-    .axi_mst_rsp_i ( axi_slv_resp        )
+    .axi_mst_rsp_i ( axi_slv_resp        ),
+    .sram_cfg_data_i('0),
+    .sram_cfg_tag_i ('0)
   );
 
   task static cycle_start;