[HW]: Add mem_multibanked_pwrgate for correct power management #296
Annotations
8 warnings
[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L24:
src/mem_multibank_pwrgate.sv#L24
Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L26:
src/mem_multibank_pwrgate.sv#L26
Explicitly define a storage type for every parameter and localparam, (SimInit). [Style: constants] [explicit-parameter-storage-type]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L28:
src/mem_multibank_pwrgate.sv#L28
Explicitly define a storage type for every parameter and localparam, (ImplKey). [Style: constants] [explicit-parameter-storage-type]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L133:
src/mem_multibank_pwrgate.sv#L133
Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L136:
src/mem_multibank_pwrgate.sv#L136
Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L146:
src/mem_multibank_pwrgate.sv#L146
All generate block statements must have a label [Style: generate-statements] [generate-label]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L151:
src/mem_multibank_pwrgate.sv#L151
Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]
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Verilog Sources
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Artifacts
Produced during runtime
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verible-linter
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521 Bytes |
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