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mem_to_banks_detailed: Fix HideStrb alignment
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@micprog
micprog committed Jul 11, 2024
1 parent e124071 commit 39524e0
Showing 1 changed file with 11 additions and 11 deletions.
22 changes: 11 additions & 11 deletions src/mem_to_banks_detailed.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -153,11 +153,11 @@ module mem_to_banks_detailed #(
assign bank_wuser_o[i] = bank_oup[i].wuser;
assign bank_we_o[i] = bank_oup[i].we;

assign zero_strobe[i] = (bank_oup[i].strb == '0);
assign zero_strobe[i] = (|bank_req[i].strb == '0);

if (HideStrb) begin : gen_hide_strb
assign bank_req_o[i] = (bank_oup[i].we && zero_strobe[i]) ? 1'b0 : bank_req_internal[i];
assign bank_gnt_internal[i] = (bank_oup[i].we && zero_strobe[i]) ? 1'b1 : bank_gnt_i[i];
assign bank_req_o[i] = (bank_oup[i].we && (|bank_oup[i].strb == '0)) ? 1'b0 : bank_req_internal[i];

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[verible-verilog-lint] src/mem_to_banks_detailed.sv#L159 

Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]"  location:{path:"./src/mem_to_banks_detailed.sv"  range:{start:{line:159  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
assign bank_gnt_internal[i] = (bank_oup[i].we && (|bank_oup[i].strb == '0)) ? 1'b1 : bank_gnt_i[i];

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[verible-verilog-lint] src/mem_to_banks_detailed.sv#L160 

Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]"  location:{path:"./src/mem_to_banks_detailed.sv"  range:{start:{line:160  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
end else begin : gen_legacy_strb
assign bank_req_o[i] = bank_req_internal[i];
assign bank_gnt_internal[i] = bank_gnt_i[i];
Expand All @@ -175,15 +175,15 @@ module mem_to_banks_detailed #(
) i_dead_write_fifo (
.clk_i,
.rst_ni,
.flush_i ( 1'b0 ),
.testmode_i ( 1'b0 ),
.full_o ( dead_write_fifo_full ),
.empty_o ( dead_write_fifo_empty ),
.flush_i ( 1'b0 ),
.testmode_i ( 1'b0 ),
.full_o ( dead_write_fifo_full ),
.empty_o ( dead_write_fifo_empty ),
.usage_o (),
.data_i ( bank_we_o & zero_strobe ),
.push_i ( req_i & gnt_o ),
.data_o ( dead_response_unmasked ),
.pop_i ( rvalid_o )
.data_i ( {NumBanks{we_i}} & zero_strobe ),
.push_i ( req_i & gnt_o ),
.data_o ( dead_response_unmasked ),
.pop_i ( rvalid_o )
);
assign dead_response = dead_response_unmasked & {NumBanks{~dead_write_fifo_empty}};
end else begin : gen_no_dead_write_fifo
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